- 12 Sep, 2016 1 commit
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Marc Zyngier authored
at91 used to set a default trigger type for GPIO interrupts in order to cope with the old board files. These days are long gone, and it all gets probed through DT. Andras Szemzo reported that the Ethernet device on his board was bailing to be probed, due to a conflict in interrupt trigger. Surely enough, this is due to this default trigger still being present, and turning this into a IRQ_TYPE_NONE fixes the issue. Reported-by:
Andras Szemzo <szemzo.andras@gmail.com> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 07 Sep, 2016 11 commits
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Milo Kim authored
H3 has single PWM channel. The second PWM channel is not supported, so the pinctrl function should be removed. Signed-off-by:
Milo Kim <woogyom.kim@gmail.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Julia Lawall authored
Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Julia Lawall authored
Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by:
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Julia Lawall authored
Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by:
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Agrawal, Nitesh-kumar authored
In the function amd_gpio_irq_set_type, use the settings provided by the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure the GPIO registers. Ignore the settings from client. Reviewed-by:
Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by:
Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> Signed-off-by:
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Mylène Josserand authored
Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by:
Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
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Andrew Jeffery authored
A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docsSigned-off-by:
Andrew Jeffery <andrew@aj.id.au> Reviewed-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
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Andrew Jeffery authored
A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docsSigned-off-by:
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Andrew Jeffery authored
The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by:
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Andrew Jeffery authored
Outline expectations on the pin controller's relationship with the System Control Unit (SCU) IP through syscon, and document the compatible strings for 4th and 5th generation Aspeed SoC pin controllers. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Martin Blumenstingl authored
sd_emmc_a is used a controller for the SDIO modules. This adds the pin configuration for the SDIO controller. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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- 05 Sep, 2016 3 commits
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Daniel Glöckner authored
It contains pin 50 instead of pin 40. Signed-off-by:
Daniel Glöckner <dg@emlix.com> Reviewed-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Add support for R-Car M3-W Add initial support for the Pin Function Controller on the Renesas R-Car M3-W SoC: - Basic definitions, - SCIF (serial) pins, groups and functions, - SDHI pins, groups and functions.
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Vladimir Zapolskiy authored
cat /sys/kernel/debug/pinctrl/${pinctrl}/pinconf-groups output is hardly readable, if a pin group contains more than one pin the output is glued and looks like this: MX6Q_PAD_SD1_DAT0: 0x17071MX6Q_PAD_SD1_CMD: 0x17071MX6Q_PAD_SD1_CLK: 0x17071 Add two space indentation and a new line separator to improve readability of the output. Signed-off-by:Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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- 27 Aug, 2016 6 commits
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Paul Gortmaker authored
The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-sirf.o --> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-sirf.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by:Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Paul Gortmaker authored
The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-atlas7.o ---> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-atlas7.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: -
Paul Gortmaker authored
The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_ROCKCHIP drivers/pinctrl/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-gpio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by:
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Paul Gortmaker authored
The Kconfig currently controlling compilation of this code is: drivers/pinctrl/nomadik/Kconfig:config PINCTRL_NOMADIK drivers/pinctrl/nomadik/Kconfig: bool "Nomadik pin controller driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alessandro Rubini <rubini@unipv.it> Cc: linux-gpio@vger.kernel.org Signed-off-by:
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Paul Gortmaker authored
The Kconfig currently controlling compilation of this code is: config PINCTRL_ABX500 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_ALIAS is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alessandro Rubini <rubini@unipv.it> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: -
Paul Gortmaker authored
The Makefile currently controlling compilation of this code is: drivers/pinctrl/mediatek/pinctrl-mtk-common.o ---> drivers/pinctrl/mediatek/Makefile:obj-y += pinctrl-mtk-common.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. We don't replace module.h with init.h since the file doesn't need that. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: linux-gpio@vger.kernel.org Signed-off-by:
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- 24 Aug, 2016 1 commit
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Neil Armstrong authored
Add support for PWM pins, for EE and AO domains. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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- 22 Aug, 2016 5 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.9 - Bias and DU support for R-Car H3, - Basic R-Car V2H support, - Cleanups and fixes.
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Martin Blumenstingl authored
This adds the IR remote receiver to the AO domain devices. Signed-off-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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LABBE Corentin authored
of_match_device could return NULL, and so cause a NULL pointer dereference later at line 1009: pinctrl_data = match->data; For fixing this problem, we use of_device_get_match_data(), this will simplify the code a little by using a standard function for getting the match data. Reported-by: coverity (CID 1324136) Signed-off-by:
LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by:
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perr perr authored
Because chained_irq_enter() has already called chip->irq_mask() and chip->irq_ack(), also chained_irq_exit() will call chip->irq_unmask(), so it's not necessary to call chip->irq_*() here. Signed-off-by:
Perr Zhang <strongbox8@zoho.com> Acked-by:
Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> [Hand-edited from whitespace damaged patch] Signed-off-by:
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Beniamino Galvani authored
The driver originally supported more domains (register ranges) per pinctrl device, but since commit 9dab1868 ("pinctrl: amlogic: Make driver independent from two-domain configuration") each device gets assigned a single domain and we instantiate multiple pinctrl devices in the DT. Therefore, now the 'meson_domain' and 'meson_domain_data' structures don't have any reason to exist and can be removed to make the model simpler to understand. This commit doesn't change behavior. Tested on a Odroid-C2. Signed-off-by:
Beniamino Galvani <b.galvani@gmail.com> Acked-by:
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- 19 Aug, 2016 3 commits
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Takeshi Kihara authored
This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Takeshi Kihara authored
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
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- 16 Aug, 2016 1 commit
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Laurent Pinchart authored
Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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- 11 Aug, 2016 4 commits
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Patrice Chotard authored
This patch allows to use the second parameter of gpio specifier, which is used to specify whether the gpio is active high or low. Simply remove specific of_xlate callback() and of_gpio_n_cells and use default one set by of_gpiochip_add() which allows to use second parameter gpio specifier. Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Julia Lawall authored
Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e1,e2,x; @@ - if (of_get_property(e1,e2,NULL)) - x = true; - else - x = false; + x = of_property_read_bool(e1,e2); // </smpl> Signed-off-by:
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Stephen Boyd authored
The drivers don't really need to know which PMIC they're for, so make a generic binding for them. This alleviates us from updating the drivers every time a new PMIC comes out. It's still recommended that we update the binding with new PMIC models and always specify the specific model for the MPPs and gpios before the generic compatible string in devicetree, but this at least cuts down on adding more and more compatible strings to the drivers until we actually need them. Cc: <devicetree@vger.kernel.org> Acked-by:
"Ivan T. Ivanov" <iivanov.xz@gmail.com> Reviewed-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Marcus Cooper authored
Add the SPDIF mux functionality to the pinctrl for the Allwinner A31 SoC. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Acked-by:
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- 08 Aug, 2016 5 commits
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Sergei Shtylyov authored
Add DU pin groups to the R8A7792 PFC driver. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by:
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Geert Uytterhoeven authored
This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by:
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Sergei Shtylyov authored
Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by:
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Sergei Shtylyov authored
Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by:
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