- 15 Jan, 2021 27 commits
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git://github.com/skeggsb/linuxDave Airlie authored
Merge branch '04.01-ampere-lite' of git://github.com/skeggsb/linux into topic/nouveau-ampere-modeset This adds support for basic modeseting on the nvidia ampere chipsets. This code should all be contained to just those and have no effect on current hardware. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv5LmMP+HbDUQBf_dy1-0eS9fA32k8HWo4y5X4-7rsw-yw@mail.gmail.com
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git://github.com/skeggsb/linuxDave Airlie authored
As requested, here's a tree with the non-Ampere-specific fixes split out, as most of them are potentially relevant to already-supported GPUs. - irq handling fix - expansion ROM fix - hw init dpcd disable - aux semaphore owner field fix - vram heap sizing fix - notifier at 0 is valid fix Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-fixes-5.11-2021-01-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.11-2021-01-14: amdgpu: - Update repo location in MAINTAINERS - Add some new renoir PCI IDs - Revert CRC UAPI changes - Revert OLED display fix which cases clocking problems for some systems - Misc vangogh fixes - GFX fix for sienna cichlid - DCN1.0 fix for pipe split - Fix incorrect PSP command amdkfd: - Fix possible out of bounds read in vcrat creation Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-intel-fixes-2021-01-14' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.11-rc4: - Allow the sysadmin to override security mitigations - Restore clear-residual mitigations for ivb/byt - Limit VFE threads based on GT - GVT: fix vfio edid and full display detection - Fix DSI DSC power refcounting - Fix LPT CPU mode backlight takeover - Disable RPM wakeref assertions during driver shutdown - Fix DSI sequence sleeps Signed-off-by:
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Ben Skeggs authored
UEFI/RM no longer use IED scripts from the VBIOS, though they appear to have been updated for use by the x86 VBIOS code, so we should be able to continue using them for the moment. Unfortunately, we require some hacks to do so, as the BeforeLinkTraining IED script became a pointer to an array of scripts instead, without a revbump of the relevant tables. There's also some changes to SOR clock divider fiddling, which are hopefully correct enough that things work as they should. AFAIK, GA100 shouldn't have display, so it hasn't been added. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Appears to be compatible with GV100 code, and not required on GA100, as it shouldn't have display. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with GM200 code. Signed-off-by: -
Ben Skeggs authored
GA100 appears to be compatible with GK104 code, the others have some register moves. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with TU102 code. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with TU102 code. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with GK20A code. Signed-off-by: -
Ben Skeggs authored
No VPR scrub. GA102 and GA104 have a new VRAM size detection method. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with NV50 code. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with GM200 code. Signed-off-by: -
Ben Skeggs authored
Fortunately, all the interrupts we need to bring up basic display support are contained in a single leaf register, allowing this basic (but hackish) implementation. There's a bunch more invasive patches to come implementing all this in a better/more complete way, but trying to get a minimal series out first. Signed-off-by: -
Ben Skeggs authored
VPLL regs changed a bit. There's more stuff to do around these, but it's less invasive to stick those changes into disp for now. None of that belongs here anymore anyhow - fix that someday. Signed-off-by: -
Ben Skeggs authored
Forcing PRAMIN-shadowing off for GA100, as it requires display, and we don't know if/where the fuse register for detecting its presence is. Signed-off-by: -
Ben Skeggs authored
Appears to be compatible with GP100 code. Signed-off-by: -
Ben Skeggs authored
VRAM offset 0 is a valid address, triggered on GA102. Signed-off-by: -
Ben Skeggs authored
GA100 hidden behind a module option, as it's not been as well verified since initial bring-up and may need additional changes. There's no display anyway, so this can wait for a bit. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Noticed while debugging GA102. Signed-off-by: -
Ben Skeggs authored
RM does this around transactions, and it seemed to help while debugging AUXCH issues on GA102. Signed-off-by: -
Ben Skeggs authored
No functional changes here yet. Signed-off-by: -
Ben Skeggs authored
Whatever it is that we were doing before doesn't work on Ampere. Signed-off-by: -
Ben Skeggs authored
This issue has generally been covered up by the presence of additional expansion ROMs after the ones we're interested in, with header fetches of subsequent images loading enough of the ROM to hide the issue. Noticed on GA102, which lacks a type 0x70 image compared to TU102,. [ 906.364197] nouveau 0000:09:00.0: bios: 00000000: type 00, 65024 bytes [ 906.381205] nouveau 0000:09:00.0: bios: 0000fe00: type 03, 91648 bytes [ 906.405213] nouveau 0000:09:00.0: bios: 00026400: type e0, 22016 bytes [ 906.410984] nouveau 0000:09:00.0: bios: 0002ba00: type e0, 366080 bytes vs [ 22.961901] nouveau 0000:09:00.0: bios: 00000000: type 00, 60416 bytes [ 22.984174] nouveau 0000:09:00.0: bios: 0000ec00: type 03, 71168 bytes [ 23.010446] nouveau 0000:09:00.0: bios: 00020200: type e0, 48128 bytes [ 23.028220] nouveau 0000:09:00.0: bios: 0002be00: type e0, 140800 bytes [ 23.080196] nouveau 0000:09:00.0: bios: 0004e400: type 70, 7168 bytes Signed-off-by: -
git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
Short summary of fixes pull: * dma-buf: Fix a memory leak in CMAV heap * drm: Fix format check for legacy pageflips * ttm: Pass correct address to dma_mapping_error(); Use mutex in pool shrinker Signed-off-by:
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- 14 Jan, 2021 13 commits
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Wayne Lin authored
[Why] Find out when we try to disable CRC calculation, crc generation is still enabled. Main reason is that dc_stream_configure_crc() will never get called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE. [How] Add checking condition that when source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE, we should also call dc_stream_configure_crc() to disable crc calculation. Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This reverts commit c920888c. Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Bindu R <Bindu.R@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
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Rodrigo Siqueira authored
This reverts commit 6ae09fa4. Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Bindu R <Bindu.R@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by:
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Rodrigo Siqueira authored
This reverts commit f01afd1e. Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Bindu R <Bindu.R@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by:
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Likun Gao authored
Add function to set power brake sequence. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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mengwang authored
add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by:
mengwang <mengbing.wang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Prike Liang authored
Add green_sardine PCI id support and map it to renoir asic type. v2: add apu flag Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Huang Rui authored
This patch is to update atomfirmware parser for the memory type and bandwidth of DDR5 and DDR4. Signed-off-by:
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chen gong authored
The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for Vnagogh are different from the others. The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by calculation. The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by calculation. Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Jeremy Cline authored
KASAN reported a slab-out-of-bounds read of size 1 in kdf_create_vcrat_image_cpu(). This occurs when, for example, when on an x86_64 with a single NUMA node because kfd_fill_iolink_info_for_cpu() is a no-op, but afterwards the sub_type_hdr->length, which is out-of-bounds, is read and multiplied by entries. Fortunately, entries is 0 in this case so the overall crat_table->length is still correct. Check if there were any entries before de-referencing sub_type_hdr which may be pointing to out-of-bounds memory. Fixes: b7b6c385 ("drm/amdkfd: Calculate CPU VCRAT size dynamically (v2)") Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Jeremy Cline <jcline@redhat.com> Reviewed-by:
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Rodrigo Siqueira authored
commit a861736d ("drm/amd/display: Fixed Intermittent blue screen on OLED panel") causes power regression for many users. It seems that this change causes the MCLK to get forced high; this creates a regression for many users since their devices were not able to drop to a low state after this change. For this reason, this reverts commit a861736d. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1407 Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Naveed Ashfaq <Naveed.Ashfaq@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Roman Li <roman.li@amd.com> Acked-by:
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Li, Roman authored
[Why] The initial purpose of dcn10 pipe split is to support some high bandwidth mode which requires dispclk greater than max dispclk. By initial bring up power measurement data, it showed power consumption is less with pipe split for dcn block. This could be reason for enable pipe split by default. By battery life measurement of some Chromebooks, result shows battery life is longer with pipe split disabled. [How] Disable pipe split by default. Pipe split could be still enabled when required dispclk is greater than max dispclk. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] Required for DSC MST Tested-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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