- 23 Feb, 2021 1 commit
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https://github.com/intel/gvt-linuxRodrigo Vivi authored
Merge tag 'gvt-next-fixes-2021-02-22' of https://github.com/intel/gvt-linux into drm-intel-next-fixes gvt-next-fixes-2021-02-22 - Fix to use i915 default state for cmd parser on all engines (Chris) - Purge dev_priv->gt (Chris) - Fix gvt object ww locking (Zhi) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210222083402.GD1551@zhen-hp.sh.intel.com
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- 22 Feb, 2021 3 commits
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Zhi Wang authored
To support ww locking and per-object implemented in i915, GVT scheduler needs to be refined. Most of the changes are located in shadow batch buffer, shadow wa context in GVT-g, where use quite a lot of i915 gem object APIs. v2: - Adjust the usage of ww lock on context pin/unpin. (maarten) - Rebase the patch on the newest staging branch. Fixes: 6b050304 ("drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2.") Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
Zhi Wang <zhi.a.wang@intel.com> Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1610314985-26065-1-git-send-email-zhi.wang.linux@gmail.comReviewed-by:
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Chris Wilson authored
Use the right intel_gt stored as a backpointer in intel_vgpu. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
Rather than break existing context objects by incorrectly forcing them to rogue cache coherency and trying to assert a new mapping, read the reg whitelist from the default context image. And use gvt->gt, never &dev_priv->gt. Fixes: 493f30cd ("drm/i915/gvt: parse init context to update cmd accessible reg whitelist") Acked-by:
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- 17 Feb, 2021 2 commits
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Chris Wilson authored
The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.7+ Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk (cherry picked from commit 1914911f4aa08ddc05bae71d3516419463e0c567) Signed-off-by:
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Ville Syrjälä authored
ilk+ planes get notably unhappy when the plane x+w exceeds the stride. This wasn't a problem previously because we always aligned SURF to the closest tile boundary so the x offset never got particularly large. But now with async flips we have to align to 256KiB instead and thus this becomes a real issue. On ilk/snb/ivb it looks like the accesses just wrap early to the next tile row when scanout goes past the SURF+n*stride boundary, hsw/bdw suffer more heavily and start to underrun constantly. i965/g4x appear to be immune. vlv/chv I've not yet checked. Let's borrow another trick from the skl+ code and search backwards for a better SURF offset in the hopes of getting the x offset below the limit. IIRC when I ran into a similar issue on skl years ago it was causing the hardware to fall over pretty hard as well. And let's be consistent and include i965/g4x in the check as well, just in case I just got super lucky somehow when I wasn't able to reproduce the issue. Not that it really matters since we still use 4k SURF alignment for i965/g4x anyway. Fixes: 6ede6b06 ("drm/i915: Implement async flips for vlv/chv") Fixes: 4bb18054 ("drm/i915: Implement async flip for ilk/snb") Fixes: 2a636e24 ("drm/i915: Implement async flip for ivb/hsw") Fixes: cda195f1 ("drm/i915: Implement async flips for bdw") Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210209021918.16234-1-ville.syrjala@linux.intel.comReviewed-by:
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- 08 Feb, 2021 7 commits
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Ville Syrjälä authored
The BXT/GLK DPLL can't generate certain frequencies. We already reject the 233-240MHz range on both. But on GLK the DPLL max frequency was bumped from 300MHz to 594MHz, so now we get to also worry about the 446-480MHz range (double the original problem range). Reject any frequency within the higher problematic range as well. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3000Signed-off-by:
Mika Kahola <mika.kahola@intel.com> (cherry picked from commit 41751b3e) Signed-off-by:
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Chris Wilson authored
Flush; invalidate; change registers; invalidate; flush. Will this finally work on every device? Or will Baytrail complain again? On the positive side, we immediately see the benefit of having hsw-gt1 in CI. Fixes: ace44e13 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals") Testcase: igt/gem_render_tiled_blits # hsw-gt1 Signed-off-by:
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Chris Wilson authored
Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as the machine stops responding milliseconds after receipt of the reset request [GDRT]. By disabling the cached atomics, the hang do not occur and we presume the GPU would reset normally for similar hangs. Sadly this is a shotgun approach, but since the impact is critical it is better to err on the safe side and work back from there. Reported-by:
Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998Signed-off-by:
Jason Ekstrand <jason@jlesktrand.net> Link: https://patchwork.freedesktop.org/patch/msgid/20210125220152.24070-1-chris@chris-wilson.co.uk Cc: stable@vger.kernel.org (cherry picked from commit b267c7ae0ad5b437b068f46919b17f85000154b4) Signed-off-by:
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Chris Wilson authored
Push the hibernate pm routines next to the suspend pm routines in gem/i915_gem_pm.c. This has the side-effect of putting the wbinvd() abusers next to each other. Reported-by:
Guenter Roeck <linux@roeck-us.net> Fixes: 30d2bfd0 ("drm/i915/gem: Almagamate clflushes on freeze") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210123145543.10533-1-chris@chris-wilson.co.uk (cherry picked from commit 6d8f02207420e76db693a00ccb44792474e297fc) Signed-off-by:
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Dan Carpenter authored
This code will Oops when it tries to i915_gem_object_free(obj) because "obj" is an error pointer. Fixes: 97d55396 ("drm/i915/region: convert object_create into object_init") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Dan Carpenter authored
Smatch found an uninitialized variable bug in this code: drivers/gpu/drm/i915/gvt/cmd_parser.c:3191 intel_gvt_update_reg_whitelist() error: uninitialized symbol 'ret'. The first thing that Smatch complains about is that "ret" isn't set if we don't enter the "for_each_engine(engine, &dev_priv->gt, id) {" loop. Presumably we always have at least one engine so that's a false positive. But it's definitely a bug to not set "ret" if i915_gem_object_pin_map() fails. Let's fix the bug and silence the false positive. Fixes: 493f30cd ("drm/i915/gvt: parse init context to update cmd accessible reg whitelist") Signed-off-by: -
Chris Wilson authored
Let's not encourage everybody to build i915's debug code, and certainly not the build robots who need to scrutinise the production build. Since CI will complain if the debug build is broken, having the other build bots focus on the builds we don't cover ourselves should improve the build coverage. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 4f86975f ("drm/i915: Add DEBUG_GEM to the recommended CI config") Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122091058.5145-1-chris@chris-wilson.co.uk (cherry picked from commit c442f658299d59b327a4bf21457ec8ece936f133) Signed-off-by:
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- 04 Feb, 2021 25 commits
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Arnd Bergmann authored
After all users of the 'dm' warnings got hidden in an #ifdef, the compiler started warning about it being unused: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable] Add another such #ifdef. Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125124849.102037-1-arnd@kernel.org
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Dave Airlie authored
Merge tag 'amd-drm-next-5.12-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-02-03: amdgpu: - Display fixes and cleanups - Vangogh fixes - Fix possible race when there are timeouts on two rings - SR-IOV fixes - Add missing license - DCE 10/12 bpc fixes - Display MALL fixes - Fix SMU user preference settings persistence - Fix retry in gem allocate - Add new PCI DID - Fix for manual fan speed control on cards where it was problematic - Fix regression in pinning GTT - Misc display fixes - Misc code cleanups amdkfd: - Fix config handling - Fix regression in buffer free From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210204045717.3823-1-alexander.deucher@amd.comSigned-off-by:
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Dave Airlie authored
Merge tag 'mediatek-drm-next-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.12 1. Decouple Mediatek DRM sub driver 2. Share mtk mutex driver for both DRM and MDP 3. Add support for SoC MT8183 Signed-off-by:
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Yongqiang Niu authored
Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by:
Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by:
CK Hu <ck.hu@mediatek.com> Signed-off-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org>
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Yongqiang Niu authored
Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by:
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Yongqiang Niu authored
ccorr ctm matrix bits will be different in mt8192. Signed-off-by:
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Yongqiang Niu authored
Enable dither function to improve the display quality. Signed-off-by:
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Yongqiang Niu authored
Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled. Signed-off-by:
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Yongqiang Niu authored
1. Add ovl private data 2. Add rdma private data 3. Add gamma privte data 4. Add main and external path module for crtc create Signed-off-by:
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Yongqiang Niu authored
Not all SoC has dither function in gamma module. Add private data to control this function setting. Signed-off-by:
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Yongqiang Niu authored
mt8183 gamma module will different with mt8173, so separate gamma for adding private data. Signed-off-by:
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Hsin-Yi Wang authored
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function. Separate necessary parameters out so other device components (dither, gamma) can call this function. Signed-off-by:
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CK Hu authored
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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CK Hu authored
Moving mutex resource management from client driver to mutex driver could prevent client drivers negotiating for resource management. Signed-off-by:
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CK Hu authored
mtk mutex is used by both drm and mdp driver, so change disp/ddp term to mutex to show that it's a common driver for drm and mdp. Signed-off-by:
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CK Hu authored
After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by:
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CK Hu authored
Those file includings are useless, so remove them. Signed-off-by:
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Yongqiang Niu authored
Get the fifo size from device tree because each rdma in the same SoC may have different fifo size Signed-off-by:
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Yongqiang Niu authored
The orginal setting is not correct, fix it to follow hardware data sheet. If keep this error setting, mt8173/mt8183 display ok but mt8192 display abnormal. Fixes: 0664d139 ("drm/mediatek: Add AAL engine basic function") Signed-off-by:
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Yongqiang Niu authored
add description for postmask postmask is used control round corner for display frame Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Hsin-Yi Wang authored
Similar to commit a9d9fea7 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by:
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Yongqiang Niu authored
rdma fifo size may be different even in same SOC, add this property to the corresponding rdma Signed-off-by:
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Yongqiang Niu authored
It's possible that state->base.fb is null. Add a check before access its format. Fixes: b6b1bb98 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
- WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) Signed-off-by:
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ssh://git.freedesktop.org/git/tegra/linuxDave Airlie authored
drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. Signed-off-by:
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- 02 Feb, 2021 2 commits
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Dan Carpenter authored
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bernard Zhao authored
Remove unneeded variable: "pattern". Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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