- 24 Nov, 2020 2 commits
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Rajendra Nayak authored
Add device tree binding Documentation details for Qualcomm SC7280 TLMM block. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1604570192-15057-1-git-send-email-rnayak@codeaurora.orgSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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John Stultz authored
One fixup following my patch commit be117ca3 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a selected config") being queued in LinusW's tree, as a new config entry was added for the msm8953 that also needs the change. Applies to LinusW's pinctrl devel tree. Signed-off-by:
John Stultz <john.stultz@linaro.org> Reviewed-by:
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- 23 Nov, 2020 1 commit
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Linus Walleij authored
This reverts commit d0511b54. After some time it was noticed that the Tegra186 among others were experiencing problems when making this into a module. Signed-off-by:
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- 17 Nov, 2020 2 commits
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Fabio Estevam authored
Since commit 4b563a06 ("ARM: imx: Remove imx21 support") the imx21 SoC is no longer supported. Get rid of its pinctrl driver too, which is now unused. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20201110190210.29376-1-festevam@gmail.comSigned-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.11 - Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H, - Image size optimizations and code consolidations, - Minor fixes and improvements.
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- 13 Nov, 2020 15 commits
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Rikard Falkeborn authored
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the ops field in the regulator_desc struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: -
Geert Uytterhoeven authored
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD) registers, like R-Car Gen3 and RZ/G2. Update the function to handle SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car Gen1/Gen2 and RZ/G1. Reduce code duplication by converting the R-Car M1A pin control driver to use the common handler. Note that this changes behavior in case the (invalid!) option "bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored silently; after this change, it is considered the same as "bias-pull-up". Signed-off-by:
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Geert Uytterhoeven authored
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car M1A uses register offsets instead of register physical addresses. This is different from the handling on other R-Car parts. Convert the bias handling from register offsets to physical addresses. This increases uniformity, and prepares for consolidation of the bias handling. Signed-off-by:
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Geert Uytterhoeven authored
All pin control drivers for R-Car Gen3 SoCs contain identical bias handling. Reduce code duplication by moving it to the common pinctrl.c code. Signed-off-by:
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Geert Uytterhoeven authored
Shrink sh_pfc_pin_config from 8 to 2 bytes: - The mux_set flag can be removed, as a non-zero mark value means the same (zero = PINMUX_RESERVED is an invalid mark value), - The gpio_enabled flag needs only a single bit, - Mark values are small integers, and can easily fit in a 15-bit bitfield. This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB. Signed-off-by: -
Geert Uytterhoeven authored
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is present in between the enum_id and name members of the sh_pfc_pin structure. Get rid of this hole by sorting the structure's members by decreasing size. This saves up to 1.5 KiB per enabled SoC, and reduces the size of a kernel including support for all R-Car Gen3 SoCs by more than 10 KiB. This has no size impact on SH and arm32. Signed-off-by:
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Geert Uytterhoeven authored
Fix a few singular vs. plural grammar issues in comments. Signed-off-by:
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Geert Uytterhoeven authored
Commit b13431ed ("pinctrl: sh-pfc: Remove incomplete flag "cfg->type"") removed the last statement in between the goto and the label. Hence remove both. Signed-off-by:
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Biju Das authored
This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs. Optimize pinctrl image size for RZ/G1[MN], when support for R-Car M2-W/M2-N (R8A779[13]) is not enabled. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-7-biju.das.jz@bp.renesas.comSigned-off-by:
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Biju Das authored
This driver supports both RZ/G1H and R-Car H2 SoCs. Optimize pinctrl image size for RZ/G1H, when support for R-Car H2 (R8A7790) is not enabled. Signed-off-by:
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Biju Das authored
This driver supports both RZ/G2E and R-Car E3 SoCs. Optimize pinctrl image size for RZ/G2E, when support for R-Car E3 (R8A77990) is not enabled. Signed-off-by:
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Biju Das authored
This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N (R8A77965) is not enabled. Signed-off-by:
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Biju Das authored
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Signed-off-by:
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Biju Das authored
This driver supports both RZ/G2H and R-Car H3 ES2 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2 (R8A77951) is not enabled. Signed-off-by:
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- 11 Nov, 2020 3 commits
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Martin Kaiser authored
Replace the two separate calls for setting the irq handler and data with a single irq_set_chained_handler_and_data() call. Signed-off-by:
Martin Kaiser <martin@kaiser.cx> Link: https://lore.kernel.org/r/20201108180144.28594-1-martin@kaiser.cxSigned-off-by:
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Vinod Koul authored
Commit be117ca3 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a dependency rather then a selected config") moved the qcom pinctrl drivers to have PINCTRL_MSM as dependency rather then a selected config, so do this change for SDX55 pinctrl driver as well. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
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Linus Walleij authored
We need a more granular distribution among funcion A and function B for the LCD pins for the Samsung GT-I9070. Provide some new pin groups so we can configure this phone properly. Link: https://lore.kernel.org/r/20201110232330.2242167-1-linus.walleij@linaro.orgSigned-off-by:
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- 10 Nov, 2020 16 commits
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Jeevan Shriram authored
Add initial Qualcomm SDX55 pinctrl driver to support pin configuration with pinctrl framework for SDX55 SoC. [ported from downstream and tidy up] Signed-off-by:
Jeevan Shriram <jshriram@codeaurora.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201109062620.14566-3-vkoul@kernel.orgSigned-off-by:
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Vinod Koul authored
Add device tree binding Documentation details for Qualcomm SDX55 pinctrl driver. Signed-off-by:
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Lars Povlsen authored
This patch adds support for Serval pinctrl, using the ocelot driver as basis. It adds pinconfig support as well, as supported by the platform. gclement: Split from a larger patch adding support all platforms in the same time. Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20201106093118.965152-5-gregory.clement@bootlin.comSigned-off-by:
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Lars Povlsen authored
This patch adds support for Luton pinctrl, using the ocelot driver as basis. It adds pinconfig support as well, as supported by the platform. gclement: Split from a larger patch adding support all platforms in the same time. Signed-off-by:
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Gregory CLEMENT authored
Add the documentation for the Microsemi Serval pinmuxing and gpio controller. Signed-off-by:
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Gregory CLEMENT authored
Add the documentation for the Microsemi Luton pinmuxing and gpio controller. Signed-off-by:
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Kaixu Xia authored
Fix the following coccicheck warning: ./drivers/pinctrl/pinctrl-ocelot.c:732:28-33: WARNING: conversion to bool not needed here Reported-by:
Tosk Robot <tencent_os_robot@tencent.com> Signed-off-by:
Kaixu Xia <kaixuxia@tencent.com> Link: https://lore.kernel.org/r/1604651795-1220-1-git-send-email-kaixuxia@tencent.comSigned-off-by:
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John Stultz authored
Allow the qcom_scm driver to be loadable as a permenent module. This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to ensure that drivers that call into the qcom_scm driver are also built as modules. While not ideal in some cases its the only safe way I can find to avoid build errors without having those drivers select QCOM_SCM and have to force it on (as QCOM_SCM=n can be valid for those drivers). Signed-off-by:
Kalle Valo <kvalo@codeaurora.org> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-3-john.stultz@linaro.orgSigned-off-by:
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John Stultz authored
Tweaks to allow pinctrl-msm code to be loadable as a module. This is needed in order to support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. This requires that we tweak Kconfigs selecting PINCTRL_MSM to also depend on QCOM_SCM || QCOM_SCM=n so that we match the module setting of QCOM_SCM. Signed-off-by:
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John Stultz authored
This patch reworks PINCTRL_MSM to be a visible option, and instead of having the various SoC specific drivers select PINCTRL_MSM, this switches those configs to depend on PINCTRL_MSM. This is useful, as it will be needed in order to cleanly support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. Without this change, we would eventually have to add dependency lines to every config that selects PINCTRL_MSM, and that would becomes a maintenance headache. We also add PINCTRL_MSM to the arm64 defconfig to avoid surprises as otherwise PINCTRL_MSM/IPQ* options previously enabled, will be off. Signed-off-by:
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Coiby Xu authored
Print the status of debounce filter as follows, $ cat /sys/kernel/debug/gpio pin129 interrupt is disabled | interrupt is masked | disable wakeup in S0i3 state | disable wakeup in S3 state | disable wakeup in S4/S5 state| input is high | pull-up is disabled | Pull-down is disabled | output is disabled | debouncing filter disabled | 0x50000 pin130 interrupt is disabled | interrupt is masked | disable wakeup in S0i3 state | disable wakeup in S3 state | disable wakeup in S4/S5 state | input is high | pull-up is disabled | Pull-down is disabled | output is disabled | debouncing filter (high) enabled | debouncing timeout is 124800 (us)| 0x503c8 Signed-off-by:
Coiby Xu <coiby.xu@gmail.com> Link: https://lore.kernel.org/r/20201105231912.69527-4-coiby.xu@gmail.comSigned-off-by:
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Paul Cercueil authored
Add the "lcd-8bit" group to the "lcd" function. As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could be modified to only contain the pins not already included in "lcd-8bit", just like how it's done for the JZ4740 and JZ4725B platforms. However, we can't do that without breaking Device Tree ABI, so in that case we have no choice but to have two groups containing the same pins. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Tested-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201101090104.5088-3-paul@crapouillou.netSigned-off-by:
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Paul Cercueil authored
Abuse the pin function pointer to store the pin function value directly, when all the pins of a group have the same function value. Now when the pointer value is <= 3 (unsigned), the pointer value is used as the pin function; otherwise it is used as a regular pointer. This drastically reduces the number of pin function tables needed, and drops .data usage by about 2 KiB. Additionally, the few pin function tables that are still around now contain u8 instead of int, since the largest number that will be stored is 3. Signed-off-by:
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Frank Wunderlich authored
mt7622 is reported by mediatek to have only 6 pwm channels so drop pindefines for 7th channel Signed-off-by:
Frank Wunderlich <frank-w@public-files.de> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20201016204019.2606-4-linux@fw-web.deSigned-off-by:
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Vladimir Lypak authored
Add device tree bindings documentation for Qualcomm MSM8953 pinctrl driver. Signed-off-by:
Vladimir Lypak <junak.pub@gmail.com> Reviewed-by:
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Vladimir Lypak authored
Add inititial pinctrl driver for MSM8953 platform. Compatible SoCs are: MSM8953, APQ8053, SDM(SDA)450, SDM(SDA)632. Based off CAF implementation. Signed-off-by:
Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by:
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- 05 Nov, 2020 1 commit
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Geert Uytterhoeven authored
On 64-bit platforms, pointer size and alignment are 64-bit, hence two 4-byte holes are present before the pins and gc members of the pinctrl_gpio_range structure. Get rid of these holes by moving the pins pointer. This reduces kernel size of an arm64 Rockchip kernel by ca. 512 bytes. Signed-off-by:
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