1. 19 Oct, 2017 2 commits
    • Suzuki K Poulose's avatar
      arm64: Fix the feature type for ID register fields · 5bdecb79
      Suzuki K Poulose authored
      Now that the ARM ARM clearly specifies the rules for inferring
      the values of the ID register fields, fix the types of the
      feature bits we have in the kernel.
      
      As per ARM ARM DDI0487B.b, section D10.1.4 "Principles of the
      ID scheme for fields in ID registers" lists the registers to
      which the scheme applies along with the exceptions.
      
      This patch changes the relevant feature bits from FTR_EXACT
      to FTR_LOWER_SAFE to select the safer value. This will enable
      an older kernel running on a new CPU detect the safer option
      rather than completely disabling the feature.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Dave Martin <dave.martin@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      5bdecb79
    • Julien Thierry's avatar
      arm64: Update fault_info table with new exception types · 3f7c86b2
      Julien Thierry authored
      Based on: ARM Architecture Reference Manual, ARMv8 (DDI 0487B.b).
      
      ARMv8.1 introduces the optional feature ARMv8.1-TTHM which can trigger a
      new type of memory abort. This exception is triggered when hardware update
      of page table flags is not atomic in regards to other memory accesses.
      Replace the corresponding unknown entry with a more accurate one.
      
      Cf: Section D10.2.28 ESR_ELx, Exception Syndrome Register (p D10-2381),
      section D4.4.11 Restriction on memory types for hardware updates on page
      tables (p D4-2116 - D4-2117).
      
      ARMv8.2 does not add new exception types, however it is worth mentioning
      that when obligatory feature RAS (optional for ARMv8.{0,1}) is implemented,
      exceptions related to "Synchronous parity or ECC error on memory access,
      not on translation table walk" become reserved and should not occur.
      Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      3f7c86b2
  2. 17 Oct, 2017 1 commit
  3. 16 Oct, 2017 8 commits
    • Lorenzo Pieralisi's avatar
      ACPI/IORT: Enable SMMUv3/PMCG IORT MSI domain set-up · 65637901
      Lorenzo Pieralisi authored
      ITS specific mappings for SMMUv3/PMCG components can be retrieved
      through special index mapping entries introduced in IORT revision C.
      
      Introduce a new API iort_set_device_domain() to set the MSI domain for
      SMMUv3/PMCG nodes (extendable to any future IORT node requiring special
      index ITS mapping entries) that represent MSI through special index
      mappings in order to enable MSI support for the devices their nodes
      represent.
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      65637901
    • Hanjun Guo's avatar
      ACPI/IORT: Add SMMUv3 specific special index mapping handling · 86456a3f
      Hanjun Guo authored
      IORT revision C introduced a mapping entry binding to describe ITS
      device ID mapping for SMMUv3 MSI interrupts.
      
      Enable the single mapping flag (ie that is used by SMMUv3 component for
      its special index mappings) for the SMMUv3 node in the IORT mapping API
      and add IORT code to handle special index mapping entry for the SMMUv3
      IORT nodes to enable their MSI interrupts. In case the ACPICA for
      SMMUv3 device ID mapping is not ready, use the ACPICA version as a guard
      for function iort_get_id_mapping_index().
      Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      [lorenzo.pieralisi@arm.com: patch split, typos fixing, rewrote the log]
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      86456a3f
    • Hanjun Guo's avatar
      ACPI/IORT: Enable special index ITS group mappings for IORT nodes · 8c8df8dc
      Hanjun Guo authored
      IORT revision C introduced SMMUv3 and PMCG MSI support by adding
      specific mapping entries in the SMMUv3/PMCG subtables to retrieve
      the device ID and the ITS group it maps to for a given SMMUv3/PMCG
      IORT node.
      
      Introduce a mapping function (ie iort_get_id_mapping_index()), that
      for a given IORT node looks up if an ITS specific ID mapping entry
      exists and if so retrieve the corresponding mapping index in the IORT
      node mapping array.
      
      Since an ITS specific index mapping can be present for an IORT
      node that is not a leaf node (eg SMMUv3 - to describe its own
      ITS device ID) special handling is required for two steps mapping
      cases such as PCI/NamedComponent--->SMMUv3--->ITS because the SMMUv3
      ITS specific index mapping entry should be skipped to prevent the
      IORT API from considering the mapping entry as a regular mapping one.
      
      If we take the following IORT topology example:
      
      |----------------------|
      |  Root Complex Node   |
      |----------------------|
      |    map entry[x]      |
      |----------------------|
      |       id value       |
      | output_reference     |
      |---|------------------|
          |
          |   |----------------------|
          |-->|        SMMUv3        |
              |----------------------|
              |     SMMUv3 dev ID    |
              |     mapping index 0  |
              |----------------------|
              |      map entry[0]    |
              |----------------------|
              |       id value       |
              | output_reference-----------> ITS 1 (SMMU MSI domain)
              |----------------------|
              |      map entry[1]    |
              |----------------------|
              |       id value       |
              | output_reference-----------> ITS 2 (PCI MSI domain)
              |----------------------|
      
      where the SMMUv3 ITS specific mapping entry is index 0 and it
      represents the SMMUv3 ITS specific index mapping entry (describing its
      own ITS device ID), we need to skip that mapping entry while carrying
      out the Root Complex Node regular mappings to prevent erroneous
      translations.
      
      Reuse the iort_get_id_mapping_index() function to detect the ITS
      specific mapping index for a specific IORT node and skip it in the IORT
      mapping API (ie iort_node_map_id()) loop to prevent considering it a
      normal PCI/Named Component ID mapping entry.
      Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      [lorenzo.pieralisi@arm.com: split patch/rewrote commit log]
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      8c8df8dc
    • Hanjun Guo's avatar
      ACPI/IORT: Look up IORT node through struct fwnode_handle pointer · 0a71d8b9
      Hanjun Guo authored
      Current IORT code provides a function (ie iort_get_fwnode())
      which looks up a struct fwnode_handle pointer through a
      struct acpi_iort_node pointer for SMMU components but it
      lacks a function that implements the reverse look-up, namely
      struct fwnode_handle* -> struct acpi_iort_node*.
      
      Devices that are not IORT named components cannot be retrieved through
      their associated IORT named component scan interface because they just
      are not represented in the ACPI namespace; the reverse look-up is
      therefore required for all platform devices that represent IORT nodes
      (eg SMMUs) so that the struct acpi_iort_node* can be retrieved from the
      struct device->fwnode pointer.
      Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      [lorenzo.pieralisi@arm.com: re-indented/rewrote the commit log]
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      0a71d8b9
    • Lorenzo Pieralisi's avatar
      ACPI/IORT: Make platform devices initialization code SMMU agnostic · 896dd2c3
      Lorenzo Pieralisi authored
      The way current IORT code initializes platform devices for SMMU nodes
      is somewhat tied (mostly for naming convention) to the SMMU nodes
      themselves but it need not be in that it is completely generic and
      can easily be made so by structures renaming and code reshuffling.
      
      Rework IORT platform devices initialization code to make the functions
      and data structures SMMU agnostic.
      
      No functional changes intended.
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      Cc: Hanjun Guo <hanjun.guo@linaro.org>
      Cc: Sudeep Holla <sudeep.holla@arm.com>
      896dd2c3
    • Lorenzo Pieralisi's avatar
      ACPI/IORT: Improve functions return type/storage class specifier indentation · e3d49392
      Lorenzo Pieralisi authored
      Some functions definition indentations are using a style that is frowned
      upon with return value type/storage class specifier in a separate line.
      
      Reindent the function definitions to fix them.
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      Cc: Hanjun Guo <hanjun.guo@linaro.org>
      Cc: Sudeep Holla <sudeep.holla@arm.com>
      e3d49392
    • Lorenzo Pieralisi's avatar
      ACPI/IORT: Remove leftover ACPI_IORT_SMMU_V3_PXM_VALID guard · 75808131
      Lorenzo Pieralisi authored
      The conditional ACPI_IORT_SMMU_V3_PXM_VALID guard around
      arm_smmu_v3_set_proximity() was added to manage a cross tree
      ACPICA merge dependency; with ACPICA changes merged in:
      
      commit c9442300 ("ACPICA: iasl: Update to IORT SMMUv3
      disassembling")
      
      the guard has become useless. Remove it.
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      Cc: Hanjun Guo <hanjun.guo@linaro.org>
      Cc: Sudeep Holla <sudeep.holla@arm.com>
      Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
      75808131
    • Arvind Yadav's avatar
      acpi/arm64: pr_err() strings should end with newlines · ee10b9c9
      Arvind Yadav authored
      pr_err() messages should terminated with a new-line to avoid
      other messages being concatenated onto the end.
      Signed-off-by: default avatarArvind Yadav <arvind.yadav.cs@gmail.com>
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
      ee10b9c9
  4. 13 Oct, 2017 2 commits
    • Julien Thierry's avatar
      arm64: use WFE for long delays · 7b77452e
      Julien Thierry authored
      The current delay implementation uses the yield instruction, which is a
      hint that it is beneficial to schedule another thread. As this is a hint,
      it may be implemented as a NOP, causing all delays to be busy loops. This
      is the case for many existing CPUs.
      
      Taking advantage of the generic timer sending periodic events to all
      cores, we can use WFE during delays to reduce power consumption. This is
      beneficial only for delays longer than the period of the timer event
      stream.
      
      If timer event stream is not enabled, delays will behave as yield/busy
      loops.
      Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      7b77452e
    • Julien Thierry's avatar
      arm_arch_timer: Expose event stream status · ec5c8e42
      Julien Thierry authored
      The arch timer configuration for a CPU might get reset after suspending
      said CPU.
      
      In order to reliably use the event stream in the kernel (e.g. for delays),
      we keep track of the state where we can safely consider the event stream as
      properly configured. After writing to cntkctl, we issue an ISB to ensure
      that subsequent delay loops can rely on the event stream being enabled.
      Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      ec5c8e42
  5. 11 Oct, 2017 2 commits
    • Mark Rutland's avatar
      arm64: docs: describe ELF hwcaps · 611a7bc7
      Mark Rutland authored
      We don't document our ELF hwcaps, leaving developers to interpret them
      according to hearsay, guesswork, or (in exceptional cases) inspection of
      the current kernel code.
      
      This is less than optimal, and it would be far better if we had some
      definitive description of each of the ELF hwcaps that developers could
      refer to.
      
      This patch adds a document describing the (native) arm64 ELF hwcaps.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Dave Martin <Dave.Martin@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      [ Updated new hwcap entries in the document ]
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      611a7bc7
    • Suzuki K Poulose's avatar
      arm64: Expose support for optional ARMv8-A features · f5e035f8
      Suzuki K Poulose authored
      ARMv8-A adds a few optional features for ARMv8.2 and ARMv8.3.
      Expose them to the userspace via HWCAPs and mrs emulation.
      
      SHA2-512  - Instruction support for SHA512 Hash algorithm (e.g SHA512H,
      	    SHA512H2, SHA512U0, SHA512SU1)
      SHA3 	  - SHA3 crypto instructions (EOR3, RAX1, XAR, BCAX).
      SM3	  - Instruction support for Chinese cryptography algorithm SM3
      SM4 	  - Instruction support for Chinese cryptography algorithm SM4
      DP	  - Dot Product instructions (UDOT, SDOT).
      
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Dave Martin <dave.martin@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      f5e035f8
  6. 09 Oct, 2017 1 commit
  7. 04 Oct, 2017 4 commits
  8. 02 Oct, 2017 7 commits
  9. 01 Oct, 2017 9 commits
    • Linus Torvalds's avatar
      Linux 4.14-rc3 · 9e66317d
      Linus Torvalds authored
      9e66317d
    • Linus Torvalds's avatar
      Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 368f8998
      Linus Torvalds authored
      Pull x86 fixes from Thomas Gleixner:
       "This contains the following fixes and improvements:
      
         - Avoid dereferencing an unprotected VMA pointer in the fault signal
           generation code
      
         - Fix inline asm call constraints for GCC 4.4
      
         - Use existing register variable to retrieve the stack pointer
           instead of forcing the compiler to create another indirect access
           which results in excessive extra 'mov %rsp, %<dst>' instructions
      
         - Disable branch profiling for the memory encryption code to prevent
           an early boot crash
      
         - Fix a sparse warning caused by casting the __user annotation in
           __get_user_asm_u64() away
      
         - Fix an off by one error in the loop termination of the error patch
           in the x86 sysfs init code
      
         - Add missing CPU IDs to various Intel specific drivers to enable the
           functionality on recent hardware
      
         - More (init) constification in the numachip code"
      
      * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        x86/asm: Use register variable to get stack pointer value
        x86/mm: Disable branch profiling in mem_encrypt.c
        x86/asm: Fix inline asm call constraints for GCC 4.4
        perf/x86/intel/uncore: Correct num_boxes for IIO and IRP
        perf/x86/intel/rapl: Add missing CPU IDs
        perf/x86/msr: Add missing CPU IDs
        perf/x86/intel/cstate: Add missing CPU IDs
        x86: Don't cast away the __user in __get_user_asm_u64()
        x86/sysfs: Fix off-by-one error in loop termination
        x86/mm: Fix fault error path using unsafe vma pointer
        x86/numachip: Add const and __initconst to numachip2_clockevent
      368f8998
    • Linus Torvalds's avatar
      Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · c42ed9f9
      Linus Torvalds authored
      Pull timer fixes from Thomas Gleixner:
       "This adds a new timer wheel function which is required for the
        conversion of the timer callback function from the 'unsigned long
        data' argument to 'struct timer_list *timer'. This conversion has two
        benefits:
      
         1) It makes struct timer_list smaller
      
         2) Many callers hand in a pointer to the timer or to the structure
            containing the timer, which happens via type casting both at setup
            and in the callback. This change gets rid of the typecasts.
      
        Once the conversion is complete, which is planned for 4.15, the old
        setup function and the intermediate typecast in the new setup function
        go away along with the data field in struct timer_list.
      
        Merging this now into mainline allows a smooth queueing of the actual
        conversion in the affected maintainer trees without creating
        dependencies"
      
      * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        um/time: Fixup namespace collision
        timer: Prepare to change timer callback argument type
      c42ed9f9
    • Linus Torvalds's avatar
      Merge branch 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 82513545
      Linus Torvalds authored
      Pull smp/hotplug fixes from Thomas Gleixner:
       "This addresses the fallout of the new lockdep mechanism which covers
        completions in the CPU hotplug code.
      
        The lockdep splats are false positives, but there is no way to
        annotate that reliably. The solution is to split the completions for
        CPU up and down, which requires some reshuffling of the failure
        rollback handling as well"
      
      * 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        smp/hotplug: Hotplug state fail injection
        smp/hotplug: Differentiate the AP completion between up and down
        smp/hotplug: Differentiate the AP-work lockdep class between up and down
        smp/hotplug: Callback vs state-machine consistency
        smp/hotplug: Rewrite AP state machine core
        smp/hotplug: Allow external multi-instance rollback
        smp/hotplug: Add state diagram
      82513545
    • Linus Torvalds's avatar
      Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 7e103ace
      Linus Torvalds authored
      Pull scheduler fixes from Thomas Gleixner:
       "The scheduler pull request comes with the following updates:
      
         - Prevent a divide by zero issue by validating the input value of
           sysctl_sched_time_avg
      
         - Make task state printing consistent all over the place and have
           explicit state characters for IDLE and PARKED so they wont be
           displayed as 'D' state which confuses tools"
      
      * 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        sched/sysctl: Check user input value of sysctl_sched_time_avg
        sched/debug: Add explicit TASK_PARKED printing
        sched/debug: Ignore TASK_IDLE for SysRq-W
        sched/debug: Add explicit TASK_IDLE printing
        sched/tracing: Use common task-state helpers
        sched/tracing: Fix trace_sched_switch task-state printing
        sched/debug: Remove unused variable
        sched/debug: Convert TASK_state to hex
        sched/debug: Implement consistent task-state printing
      7e103ace
    • Linus Torvalds's avatar
      Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 1c6f705b
      Linus Torvalds authored
      Pull perf fixes from Thomas Gleixner:
      
       - Prevent a division by zero in the perf aux buffer handling
      
       - Sync kernel headers with perf tool headers
      
       - Fix a build failure in the syscalltbl code
      
       - Make the debug messages of perf report --call-graph work correctly
      
       - Make sure that all required perf files are in the MANIFEST for
         container builds
      
       - Fix the atrr.exclude kernel handling so it respects the
         perf_event_paranoid and the user permissions
      
       - Make perf test on s390x work correctly
      
      * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        perf/aux: Only update ->aux_wakeup in non-overwrite mode
        perf test: Fix vmlinux failure on s390x part 2
        perf test: Fix vmlinux failure on s390x
        perf tools: Fix syscalltbl build failure
        perf report: Fix debug messages with --call-graph option
        perf evsel: Fix attr.exclude_kernel setting for default cycles:p
        tools include: Sync kernel ABI headers with tooling headers
        perf tools: Get all of tools/{arch,include}/ in the MANIFEST
      1c6f705b
    • Linus Torvalds's avatar
      Merge branch 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 1de47f3c
      Linus Torvalds authored
      Pull  locking fixes from Thomas Gleixner:
       "Two fixes for locking:
      
         - Plug a hole the pi_stat->owner serialization which was changed
           recently and failed to fixup two usage sites.
      
         - Prevent reordering of the rwsem_has_spinner() check vs the
           decrement of rwsem count in up_write() which causes a missed
           wakeup"
      
      * 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        locking/rwsem-xadd: Fix missed wakeup due to reordering of load
        futex: Fix pi_state->owner serialization
      1de47f3c
    • Linus Torvalds's avatar
      Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 3d9d62b9
      Linus Torvalds authored
      Pull irq fixes from Thomas Gleixner:
      
       - Add a missing NULL pointer check in free_irq()
      
       - Fix a memory leak/memory corruption in the generic irq chip
      
       - Add missing rcu annotations for radix tree access
      
       - Use ffs instead of fls when extracting data from a chip register in
         the MIPS GIC irq driver
      
       - Fix the unmasking of IPI interrupts in the MIPS GIC driver so they
         end up at the target CPU and not at CPU0
      
      * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        irq/generic-chip: Don't replace domain's name
        irqdomain: Add __rcu annotations to radix tree accessors
        irqchip/mips-gic: Use effective affinity to unmask
        irqchip/mips-gic: Fix shifts to extract register fields
        genirq: Check __free_irq() return value for NULL
      3d9d62b9
    • Linus Torvalds's avatar
      Merge branch 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 156069f8
      Linus Torvalds authored
      Pull objtool fixes from Thomas Gleixner:
       "Two small fixes for objtool:
      
         - Support frame pointer setup via 'lea (%rsp), %rbp' which was not
           yet supported and caused build warnings
      
         - Disable unreacahble warnings for GCC4.4 and older to avoid false
           positives caused by the compiler itself"
      
      * 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        objtool: Support unoptimized frame pointer setup
        objtool: Skip unreachable warnings for GCC 4.4 and older
      156069f8
  10. 30 Sep, 2017 4 commits