1. 14 Mar, 2018 3 commits
    • Jackie Li's avatar
      drm/i915: Add support to return CNL specific reserved WOPCM size · 5cbc1e2f
      Jackie Li authored
      CNL has its specific reserved GuC WOPCM size for RC6 and other hardware
      contexts.
      
      This patch updates the code to return CNL specific reserved GuC WOPCM size
      for RC6 and other hardware contexts so that the GuC WOPCM size can be
      calculated correctly for CNL.
      
      v9:
       - Created a new patch for these changes originally made in v8 4/6 patch of
         this series (Sagar/Michal)
      
      v10:
       - Used if-else ladder to the returning of context sizes (Joonas)
      
      v11:
       - Removed GUC_ prefix from context size macro (Michal)
      
      v13:
        - Updated the ordering of s-o-b/cc/r-b tags (Sagar)
      
      Bspec: 12690
      Signed-off-by: default avatarJackie Li <yaodong.li@intel.com>
      Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
      Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v12)
      Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1520987574-19351-3-git-send-email-yaodong.li@intel.com
      5cbc1e2f
    • Jackie Li's avatar
      drm/i915: Implement dynamic GuC WOPCM offset and size calculation · 6b0478fb
      Jackie Li authored
      Hardware may have specific restrictions on GuC WOPCM offset and size. On
      Gen9, the value of the GuC WOPCM size register needs to be larger than the
      value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
      reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
      will lead to GuC firmware execution failures. On the other hand, with
      current static GuC WOPCM offset and size values (512KB for both offset and
      size), the GuC WOPCM size verification will fail on Gen9 even if it can be
      fixed by lowering the GuC WOPCM offset by calculating its value based on
      HuC firmware size (which is likely less than 200KB on Gen9), so that we can
      have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
      size check.
      
      This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
      24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
      to verify the GuC WOPCM size aganist the Gen9 hardware restrictions. To
      meet all above requirements, let's provide dynamic partitioning of the
      WOPCM that will be based on platform specific HuC/GuC firmware sizes.
      
      v2:
       - Removed intel_wopcm_init (Ville/Sagar/Joonas)
       - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
       - Removed unnecessary function calls (Joonas)
       - Init GuC WOPCM partition as soon as firmware fetching is completed
      
      v3:
       - Fixed indentation issues (Chris)
       - Removed layering violation code (Chris/Michal)
       - Created separat files for GuC wopcm code  (Michal)
       - Used inline function to avoid code duplication (Michal)
      
      v4:
       - Preset the GuC WOPCM top during early GuC init (Chris)
       - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed
      
      v5:
       - Moved GuC DMA WOPCM register updating code into intel_wopcm.c
       - Took care of the locking status before writing to GuC DMA
         Write-Once registers. (Joonas)
      
      v6:
       - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)
      
      v8:
       - Updated comments and fixed naming issues (Sagar/Joonas)
       - Updated commit message to include more description about the hardware
         restriction on GuC WOPCM size (Sagar)
      
      v9:
       - Minor changes variable names and code comments (Sagar)
       - Added detailed GuC WOPCM layout drawing (Sagar/Michal)
       - Refined macro definitions to be reader friendly (Michal)
       - Removed redundent check to valid flag (Michal)
       - Unified first parameter for exported GuC WOPCM functions (Michal)
       - Refined the name and parameter list of hardware restriction checking
         functions (Michal)
      
      v10:
       - Used shorter function name for internal functions (Joonas)
       - Moved init-ealry function into c file (Joonas)
       - Consolidated and removed redundant size checks (Joonas/Michal)
       - Removed unnecessary unlikely() from code which is only called once
         during boot (Joonas)
       - More fixes to kernel-doc format and content (Michal)
       - Avoided the use of PAGE_MASK for 4K pages (Michal)
       - Added error log messages to error paths (Michal)
      
      v11:
       - Replaced intel_guc_wopcm with more generic intel_wopcm and attached
         intel_wopcm to drm_i915_private instead intel_guc (Michal)
       - dynamic calculation of GuC non-wopcm memory start (a.k.a WOPCM Top
         offset from GuC WOPCM base) (Michal)
       - Moved WOPCM marco definitions into .c source file (Michal)
       - Exported WOPCM layout diagram as kernel-doc (Michal)
      
      v12:
       - Updated naming, function kernel-doc to align with new changes (Michal)
      
      v13:
       - Updated the ordering of s-o-b/cc/r-b tags (Sagar)
       - Corrected one tense error in comment (Sagar)
       - Corrected typos and removed spurious comments (Joonas)
      
      Bspec: 12690
      Signed-off-by: default avatarJackie Li <yaodong.li@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
      Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: John Spotswood <john.a.spotswood@intel.com>
      Cc: Oscar Mateo <oscar.mateo@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
      Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v12)
      Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1520987574-19351-2-git-send-email-yaodong.li@intel.com
      6b0478fb
    • Jackie Li's avatar
      drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset · 3c009e3c
      Jackie Li authored
      GuC related exported functions should start with "intel_guc_" prefix and
      pass intel_guc as the first parameter since its GuC related. Current
      guc_ggtt_offset() failed to follow this code convention and this is a
      problem for future patches that needs to access intel_guc data to verify
      the GGTT offset against the GuC WOPCM top.
      
      This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
      the related code to pass intel_guc pointer to this function call, so that
      we can have a unified coding style for GuC code and also enable the future
      patches to get GuC related data from intel_guc to do the offset
      verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
      intel_guc_regs.h to intel_guc.h since it is not GuC register related
      definition.
      
      v8:
       - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
       - Updated commit message to explain to reason and motivation to add
         intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)
      
      v9:
       - Fixed code alignment issue due to line break (Chris)
      
      v10:
       - Removed unnecessary comments, redundant code and avoided reuse variable
         to avoid potential issues (Joonas)
      
      v13:
       - Updated the ordering of s-o-b/cc/r-b tags (Sagar)
      Signed-off-by: default avatarJackie Li <yaodong.li@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
      Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v12)
      Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1520987574-19351-1-git-send-email-yaodong.li@intel.com
      3c009e3c
  2. 13 Mar, 2018 10 commits
  3. 12 Mar, 2018 4 commits
  4. 09 Mar, 2018 15 commits
  5. 08 Mar, 2018 8 commits
    • Chris Wilson's avatar
      drm/i915: Index the ring frequency table by HW frequency range · d586b5f4
      Chris Wilson authored
      When reporting the frequency table stored in the punit, report the full
      range and not just the user restricted frequency range. In the process
      keep the code to set the frequency table and read it the same.
      
      v3: As we haven't separated the sb_lock from the pcu_lock yet, there's a
      cycle between the pcu_lock and intel_runtime_pm_get.
      
      References: f936ec34 ("drm/i915/skl: Updated the i915_ring_freq_table debugfs function")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> #v1
      Link: https://patchwork.freedesktop.org/patch/msgid/20180308142648.4016-2-chris@chris-wilson.co.uk
      d586b5f4
    • Chris Wilson's avatar
      drm/i915: Kick the rps worker when changing the boost frequency · 59cd31f1
      Chris Wilson authored
      The boost frequency is only applied from the RPS worker while someone is
      waiting on a request and requested a boost. As such, when the user
      wishes to change the frequency, we have to kick the worker in order to
      re-evaluate whether to apply the boost frequency.
      
      v2: Check num_waiters to decide if we should kick the worker to handle
      boosting.
      
      Fixes: 29ecd78d ("drm/i915: Define a separate variable and control for RPS waitboost frequency")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180308142648.4016-1-chris@chris-wilson.co.uk
      59cd31f1
    • Maarten Lankhorst's avatar
      drm/i915: Handle pipe CRC around enabling/disabling pipe. · 033b7a23
      Maarten Lankhorst authored
      This will get rid of the following error:
      [   74.730271] WARNING: CPU: 4 PID: 0 at drivers/gpu/drm/drm_vblank.c:614 drm_calc_vbltimestamp_from_scanoutpos+0x13e/0x2f0
      [   74.730311] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 x86_pkg_temp_thermal intel_powerclamp coretemp snd_hda_intel crct10dif_pclmul snd_hda_codec crc32_pclmul snd_hwdep broadcom ghash_clmulni_intel snd_hda_core bcm_phy_lib snd_pcm tg3 lpc_ich mei_me mei prime_numbers
      [   74.730353] CPU: 4 PID: 0 Comm: swapper/4 Tainted: G     U           4.16.0-rc2-CI-CI_DRM_3822+ #1
      [   74.730355] Hardware name: Dell Inc. XPS 8300  /0Y2MRG, BIOS A06 10/17/2011
      [   74.730359] RIP: 0010:drm_calc_vbltimestamp_from_scanoutpos+0x13e/0x2f0
      [   74.730361] RSP: 0018:ffff88022fb03d10 EFLAGS: 00010086
      [   74.730365] RAX: ffffffffa0291d20 RBX: ffff88021a180000 RCX: 0000000000000001
      [   74.730367] RDX: ffffffff820e7db8 RSI: 0000000000000001 RDI: ffffffff82068cea
      [   74.730369] RBP: ffff88022fb03d70 R08: 0000000000000000 R09: ffffffff815d26d0
      [   74.730371] R10: 0000000000000000 R11: ffffffffa0161ca0 R12: 0000000000000001
      [   74.730373] R13: ffff880212448008 R14: ffff880212448330 R15: 0000000000000000
      [   74.730376] FS:  0000000000000000(0000) GS:ffff88022fb00000(0000) knlGS:0000000000000000
      [   74.730378] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [   74.730380] CR2: 000055edcbec9000 CR3: 0000000002210001 CR4: 00000000000606e0
      [   74.730382] Call Trace:
      [   74.730385]  <IRQ>
      [   74.730397]  drm_get_last_vbltimestamp+0x36/0x50
      [   74.730401]  drm_update_vblank_count+0x64/0x240
      [   74.730409]  drm_crtc_accurate_vblank_count+0x41/0x90
      [   74.730453]  display_pipe_crc_irq_handler+0x176/0x220 [i915]
      [   74.730497]  i9xx_pipe_crc_irq_handler+0xfe/0x150 [i915]
      [   74.730537]  ironlake_irq_handler+0x618/0xa30 [i915]
      [   74.730548]  __handle_irq_event_percpu+0x3c/0x340
      [   74.730556]  handle_irq_event_percpu+0x1b/0x50
      [   74.730561]  handle_irq_event+0x2f/0x50
      [   74.730566]  handle_edge_irq+0xe4/0x1b0
      [   74.730572]  handle_irq+0x11/0x20
      [   74.730576]  do_IRQ+0x5e/0x120
      [   74.730584]  common_interrupt+0x84/0x84
      [   74.730586]  </IRQ>
      [   74.730591] RIP: 0010:cpuidle_enter_state+0xaa/0x350
      [   74.730593] RSP: 0018:ffffc9000008beb8 EFLAGS: 00000212 ORIG_RAX: ffffffffffffffde
      [   74.730597] RAX: ffff880226b80040 RBX: 000000000031fc3e RCX: 0000000000000001
      [   74.730599] RDX: 0000000000000000 RSI: ffffffff8210fb59 RDI: ffffffff820c02e7
      [   74.730601] RBP: 0000000000000004 R08: 00000000000040af R09: 0000000000000018
      [   74.730603] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000004
      [   74.730606] R13: ffffe8ffffd00430 R14: 0000001166120bf4 R15: ffffffff82294460
      [   74.730621]  ? cpuidle_enter_state+0xa6/0x350
      [   74.730629]  do_idle+0x188/0x1d0
      [   74.730636]  cpu_startup_entry+0x14/0x20
      [   74.730641]  start_secondary+0x129/0x160
      [   74.730646]  secondary_startup_64+0xa5/0xb0
      [   74.730660] Code: e1 48 c7 c2 b8 7d 0e 82 be 01 00 00 00 48 c7 c7 ea 8c 06 82 e8 64 ec ff ff 48 8b 83 c8 07 00 00 48 83 78 28 00 0f 84 e2 fe ff ff <0f> 0b 45 31 ed e9 db fe ff ff 41 b8 d3 4d 62 10 89 c8 6a 03 41
      [   74.730754] ---[ end trace 14b1345705b68565 ]---
      
      Changes since v1:
      - Don't try to apply CRC workaround when enabling pipe, it should already be enabled.
      Changes since v2:
      - Make crc functions for !DEBUGFS case inline.
      - Pass intel_crtc to crc functions.
      - Add comments to callsites.
      Changes since v3:
      - Cache selected source to pipe_crc->source.
      - Set pipe_crc->skipped to MIN_INT during disable to close a race condition.
      Changes since v4:
      - Handle fallout from setting pipe_crc->source in irq handler.
      
      Cc: Marta Löfstedt <marta.lofstedt@intel.com>
      Reported-by: default avatarMarta Löfstedt <marta.lofstedt@intel.com>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105185Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180308120202.52446-1-maarten.lankhorst@linux.intel.comReviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      033b7a23
    • Chris Wilson's avatar
      drm/i915: Only prune fences after wait-for-all · fa73055b
      Chris Wilson authored
      Currently, we only allow ourselves to prune the fences so long as
      all the waits completed (i.e. all the fences we checked were signaled),
      and that the reservation snapshot did not change across the wait.
      However, if we only waited for a subset of the reservation object, i.e.
      just waiting for the last writer to complete as opposed to all readers
      as well, then we would erroneously conclude we could prune the fences as
      indeed although all of our waits were successful, they did not represent
      the totality of the reservation object.
      
      v2: We only need to check the shared fences due to construction (i.e.
      all of the shared fences will be later than the exclusive fence, if
      any).
      
      Fixes: e54ca977 ("drm/i915: Remove completed fences after a wait")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Matthew Auld <matthew.auld@intel.com>
      Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180307171303.29466-1-chris@chris-wilson.co.uk
      fa73055b
    • Joonas Lahtinen's avatar
    • Joonas Lahtinen's avatar
      Merge tag 'gvt-next-2018-03-08' of https://github.com/intel/gvt-linux into drm-intel-next-queued · ed5c94a8
      Joonas Lahtinen authored
      gvt-next-2018-03-08
      
      - big refactor for shadow ppgtt (Changbin)
      - KBL context save/restore via LRI cmd (Weinan)
      - misc smatch fixes (Zhenyu)
      - Properly unmap dma for guest page (Changbin)
      - other misc fixes (Xiong, etc.)
      Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180308023152.oi4ialn5uxetbruf@zhen-hp.sh.intel.com
      ed5c94a8
    • Weinan Li's avatar
      drm/i915: add schedule out notification of preempted but completed request · 702791f7
      Weinan Li authored
      There is one corner case missing schedule out notification of the preempted
      request. The preempted request is just completed when preemption happen,
      then it will be canceled and won't be resubmitted later, GVT-g will lost
      the schedule out notification.
      
      Here add schedule out notification if found the preempted request has been
      completed.
      
      v2:
      - refine description, add completed check and notification in
        execlists_cancel_port_requests. (Chris)
      
      v3:
      - use ternary confitional, remove local variable. (Tvrtko)
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarWeinan Li <weinan.z.li@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1520302557-25079-1-git-send-email-weinan.z.li@intel.com
      702791f7
    • Lionel Landwerlin's avatar
      drm/i915: expose rcs topology through query uAPI · c822e059
      Lionel Landwerlin authored
      With the introduction of asymmetric slices in CNL, we cannot rely on
      the previous SUBSLICE_MASK getparam to tell userspace what subslices
      are available. Here we introduce a more detailed way of querying the
      Gen's GPU topology that doesn't aggregate numbers.
      
      This is essential for monitoring parts of the GPU with the OA unit,
      because counters need to be normalized to the number of
      EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
      not gives us sufficient information.
      
      The Mesa series making use of this API is :
      
          https://patchwork.freedesktop.org/series/38795/
      
      As a bonus we can draw representations of the GPU :
      
          https://imgur.com/a/vuqpa
      
      v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
          Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
          Add uapi macros to read data from *_info structs (Tvrtko)
      
      v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)
      
      v4: factorize query item writting (Tvrtko)
          tweak uapi struct/define names (Tvrtko)
      
      v5: Replace ALIGN() macro (Chris)
      
      v6: Updated uapi comments (Tvrtko)
          Moved flags != 0 checks into vfuncs (Tvrtko)
      
      v7: Use access_ok() before copying anything, to avoid overflows (Chris)
          Switch BUG_ON() to GEM_WARN_ON() (Tvrtko)
      
      v8: Tweak uapi comments style to match the coding style (Lionel)
      
      v9: Fix error in comment about computation of enabled subslice (Tvrtko)
      
      v10: Fix/update comments in uAPI (Sagar)
      
      v11: Drop drm_i915_query_(slice|subslice|eu)_info in favor of a single
           drm_i915_query_topology_info (Joonas)
      
      v12: Add subslice_stride/eu_stride in drm_i915_query_topology_info (Joonas)
      
      v13: Fix comment in uAPI (Joonas)
      Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-7-lionel.g.landwerlin@intel.com
      c822e059