- 19 Feb, 2018 40 commits
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Christian König authored
On CZ and newer APUs we can pin the fb into GART as well as VRAM. v2: Don't enable gpu_vm_support for Raven yet since it leads to a black screen. Need to debug this further before enabling. Signed-off-by:Christian König <christian.koenig@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
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Yong Zhao authored
The new register settings are needed to fix a tlb invalidation issue when MMHUB power gating is turned on for Raven. Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Eric Huang <JinhuiEric.Huang@amd.com> Reviewed-by:
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Krunoslav Kovac authored
We assume FP16 1.0 frame buffer value maps to 80 nits. DC changes are to make this configurable. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Bernstein authored
Update dcn10_init_hw such that initialization of relevant HW blocks for Maximus FPGA are also initialized (and not skipped). Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Leo (Sunpeng) Li authored
Implement the timing generator hooks for configure_crc and get_crc. Also implement is_tg_enabled, as configure_crc uses it. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
Add interfaces in DC for per CRTC CRC configuration and fetching. Also implement amdgpu_dm functions to hook onto DRM. Signed-off-by:
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Eric Bernstein authored
Cleanup to remove unused register definition from hw sequencer header file since implementation moved from hw sequencer to dchubub file. Signed-off-by:
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Yongqiang Sun authored
No need to use loop find opp, use opp in stream_res. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Roman Li authored
Fixing regression introduced by 'Use real BE and FE index to program regs.' Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Yongqiang Sun authored
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Harry Wentland authored
It's unused since the drm_edid_to_eld cleanup Signed-off-by:
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Andrew Jiang authored
We no longer change the plane state pointer for full updates, and as such, we weren't setting the input transfer function and programming the degamma registers when we are supposed to. Check for a full update, an input TF change, or a gamma change in the update flags instead to correct this. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Nikola Cornij authored
This will allow us to clean up resources on a stream as needed. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Harry Wentland authored
We've got a helper function to call dc_create_stream_for_sink and one other place that calls it directly. Make sure we call the helper functions always since we need to update a bunch of things in stream and don't want to miss that. Signed-off-by:
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Harry Wentland authored
It would be useful to know which clocks are unsupported when logging an error message about unsupported clocks. Signed-off-by:
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Yongqiang Sun authored
In case of some pipes are fused, pipe_idx should not be used to program pipe regs. Instead of that, BE and FE inst number should be used for reg index. Signed-off-by:
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Yongqiang Sun authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
Our APUs (Carrizo, Stoney, Raven) don't support it. v2: Don't use is_apu as other ASICs might also not support it Signed-off-by:
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Harry Wentland authored
It might be good to understand why validate fails. Signed-off-by:
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Yongqiang Sun authored
Proper sequence should be: disable backlight dp blank disable output edp power off In enable accelatate mode, all the encoder and controller are disabled, so move disable eDP to the function is the easiest way to implement. Signed-off-by:
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Tony Cheng authored
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Harry Wentland authored
This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
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Yongqiang Sun authored
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Krunoslav Kovac authored
Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Mikita Lipski authored
Verify that the stream is master - and program only the slave displays Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Roman Li authored
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by:
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Yongqiang Sun authored
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Jerry (Fangzhi) Zuo authored
When topology changed and rehook up MST display to the same DP connector, need to take care of drm_dp_mst_port object. Due to the topology is changed, drm_dp_mst_port and corresponding i2c_algorithm object could be NULL in such situation. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Roman Li authored
After reworking FBC init for dynamic mem alloc old FBC init code in DC became redundant. Removing it. Signed-off-by:
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Roman Li authored
- FBC init reworked to alloc memory based on display mode. - Removed asic-dependencies from dm Signed-off-by:
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Ken Chalmers authored
This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Ken Chalmers authored
Maximus testing now defaults to a 700 MHz emulated dispclk Signed-off-by:
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Charlene Liu authored
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