- 06 Dec, 2017 40 commits
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Feifei Xu authored
Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Feifei Xu authored
Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h. Signed-off-by:
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Feifei Xu authored
Remove asic/vega10/UMC folder. Signed-off-by:
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Feifei Xu authored
Cleanup asic_reg/vega10/THM folder. Signed-off-by:
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Feifei Xu authored
Cleanup asic_reg/vega10/ATHUB folder,remove unused files. Signed-off-by:
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Feifei Xu authored
Cleanup asic_reg/vega10/MP folder, remove mp_9_0_default.h Signed-off-by:
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Feifei Xu authored
Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h Signed-off-by:
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Feifei Xu authored
To remove include/asic_reg/vega10 folder,create IP folders sdma0/1. This patch cleanup asic_reg/vega10/SDMA folders. Signed-off-by:
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Monk Liu authored
found RING0 test fail after S3 resume regression, which is introduced by 1cfd8e237f0318e330190ac21d63c58ae6a1f66c Because after suspend VRAM will be cleared, so driver must unpin the GART table(resident in VRAM) during suspend so it can be evicted to system ram and must correspondingly pin it during resume so the GART table could be restored to VRAM. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Roger He authored
e.g. shrink reqeust is less than 512, the logic will skip huge pool Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Roger He authored
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Roger He authored
Reviewed-by:
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Andrew Jiang authored
On S3 resume, we do not reconstruct OPP, but we do need to reinitialize some of its values to the default ones. Therefore, move those lines out of the OPP constructor and into init_hw. Also reset the hubp power gated flag, since nothing is power gated at init_hw. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Tony Cheng authored
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Anthony Koo authored
Remove some globals that should really be per block state. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Yongqiang Sun authored
For scaling and position change, it isn't necessary to program watermark and check P-State as well. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Andrew Jiang authored
Doing bandwidth validation implies that this is a full update. Set the flag inside the function in case whatever is calling dcn_validate_bandwidth doesn't set it. Signed-off-by:
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Leo (Sunpeng) Li authored
The sequence of front-end > back-end > front-end programming will program the front-end more than once. Add a mode_changed flag, and use it to determine whether the front-end should be programmed before, or after back-end. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
With the optimized DCN10 frontend programming code, things are programmed only when requested. For now, trigger a full update on all plane changes. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
There was an error in translation of mode support check. "N/A" is a failure condition while "" was a special case. This change will differentiate between the two by using a define. Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
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Yue Hin Lau authored
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Yongqiang Sun authored
dcn10_translate_regamma_to_hw_format costs 750us to run, it cannot be called within isr, check update flag before calling, only do it for full update. Signed-off-by:
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Tony Cheng authored
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Harry Wentland authored
None of this needs to be a function table or dynamic in any way. Signed-off-by:
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Yue Hin Lau authored
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Yongqiang Sun authored
Check update flags and update dchub and dpp as per flags, reduce reg access from 347 to 200, duration time reduce to 170us. Signed-off-by:
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Yongqiang Sun authored
Move update_plane_addr to apply_ctx_for_surface, address update will just be called once, not twice for updat type is full and medium. This will reduce some reg access and duration time. Signed-off-by:
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Yue Hin Lau authored
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Michel Dänzer authored
It was incorrectly referencing the dc parameter, resulting in an empty description of the dc_log parameter. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Michel Dänzer authored
Prevent buggy userspace from spamming dmesg. Reviewed-by:
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Christian König authored
Let userspace know how much area we have above the 48bit VA hole on Vega10. Signed-off-by:
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Christian König authored
Userspace buggy userspace can spam the logs. Signed-off-by:
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Christian König authored
Similar to the CPU address space the VA on Vega10 has a hole in it. v2: use dev_dbg instead of dev_err v3: add some more comments to explain how the hw works Signed-off-by:
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Christian König authored
Instead of the global statistics use the per context bytes moved counter. v2: rebased Signed-off-by:
Dieter Nützel <Dieter@nuetzel-hh.de> Tested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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