- 08 Feb, 2021 2 commits
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Ofir Bitton authored
Current messaging communictaion protocol with cpucp can get out of sync due to coherency issues. In order to improve the protocol reliability, we modify the protocol to expect a different acknowledgment for every packet sent to cpucp. Signed-off-by:
Ofir Bitton <obitton@habana.ai> Reviewed-by:
Oded Gabbay <ogabbay@kernel.org> Signed-off-by:
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Oded Gabbay authored
Need to add ull suffix to constant when doing shift of constant into 64-bit variables Signed-off-by:
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- 06 Feb, 2021 4 commits
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Alexander Usyskin authored
Implement HBM message protocol to setup and tear down DMA buffer on behalf of an client. On top there DMA buffer allocation and its life time management. Signed-off-by:
Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20210206144325.25682-5-tomas.winkler@intel.comSigned-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Alexander Usyskin authored
Define structures for client DMA HBM protocol. The protocol requires passing dma buffer address and the buffer id. Signed-off-by:
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Alexander Usyskin authored
Client DMA capability indicates whether the firmware supports setting up a direct DMA channel between the host and me client. The DMA capabilities are supported from firmware HBM version 2.2 and newer. Signed-off-by:
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Alexander Usyskin authored
Introduce new intermediate state to allow the clients on the bus to communicate with the firmware from the remove handler. This is to enable to perform a clean shutdown. Signed-off-by:
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- 05 Feb, 2021 8 commits
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Greg Kroah-Hartman authored
Merge tag 'mhi-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-misc-next Manivannan writes: MHI changes for v5.12 Loic improved the MHI PCI generic controller by adding support for DIAG channel, PCI error handling, suspend/recovery/resume, and health check. Loic also added support for resetting the MHI device as per the MHI specification. This includes writing to a specific register for default cases and looking for controller specific callback when provided. Along with this Loic, also added a new API which gets the number for free TREs (Transfer Ring Elements) from the MHI core. The client drivers can make use of this API and the current consumer is the "mhi-net" driver. For taking both the "mhi-net" driver change and the API change, we created "mhi-net-immutable" branch for this patch and merged the same into net-next and mhi-next. Carl added a patch which lets the controller driver to pass the custom IRQ flags for BHI and MHI event interrupts to the MHI core. The current consumer of this feature is the ath11k MHI controller driver. For taking both the changes, we created "mhi-ath11k-immutable" branch for this patch and merged into ath11k-next and mhi-next. Finally, Loic cleaned up the MHI queue APIs and fixed the shared MSI vector support. * tag 'mhi-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi: bus: mhi: pci_generic: Increase num of elements in hw event ring mhi: pci_generic: Print warning in case of firmware crash bus: mhi: core: Add helper API to return number of free TREs mhi: core: Factorize mhi queuing mhi: use irq_flags if controller driver configures it mhi: pci_generic: Fix shared MSI vector support mhi: unconstify mhi_event_config bus: mhi: Ensure correct ring update ordering with memory barrier mhi: pci_generic: Set irq moderation value to 1ms for hw channels mhi: pci_generic: Add diag channels mhi: pci_generic: Increase controller timeout value mhi: pci_generic: Add health-check mhi: pci_generic: Add PCI error handlers mhi: pci_generic: Add suspend/resume/recovery procedure mhi: pci_generic: Add support for reset mhi: pci_generic: Enable burst mode for hardware channels mhi: pci-generic: Increase number of hardware events bus: mhi: core: Add device hardware reset support
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Uwe Kleine-König authored
This was non-trivial to get right because commits c23bc382 ("coresight: etm4x: Refactor probing routine") and 5214b563 ("coresight: etm4x: Add support for sysreg only devices") changed the code flow considerably. With this change the driver can be built again. Fixes: 0573d3fa ("Merge branch 'devel-stable' of git://git.armlinux.org.uk/~rmk/linux-arm into char-misc-next") Signed-off-by:
Uwe Kleine-König <uwe@kleine-koenig.org> Link: https://lore.kernel.org/r/20210205130848.20009-1-uwe@kleine-koenig.orgSigned-off-by:
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Loic Poulain authored
We met some sporadic modem crashes during high throughput testing, this has been root caused to a lack of elements in the event ring. Indeed, the modem is simply crashing when event ring becomes empty. It appears that the total number event ring elements is too low given the performances of the modem (IPA hardware accelerator). This change increases the number of elements in the hardware event ring to 2048, which is aligned with what is defined in downstream version: https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi?h=msm-4.14#n482 With this change, modem coes not crash anymore. Note: An event ring element is 16-Byte, so the total memory usage of a hardware event ring is now 32KB. Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1612514195-8257-1-git-send-email-loic.poulain@linaro.orgSigned-off-by:
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Loic Poulain authored
Print warning when MHI detects sys error. Signed-off-by:
Hemant Kumar <hemantk@codeaurora.org> Reviewed-by:
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Subbaraman Narayanamurthy authored
"sdam->pdev" is uninitialized and it is used to print error logs. Fix it. Since device pointer can be used from sdam_config, use it directly thereby removing pdev pointer. Fixes: 40ce9798 ("nvmem: add QTI SDAM driver") Cc: stable@vger.kernel.org Signed-off-by:
Subbaraman Narayanamurthy <subbaram@codeaurora.org> Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210205100853.32372-3-srinivas.kandagatla@linaro.orgSigned-off-by:
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Nicolas Saenz Julienne authored
s/drivers/driver/ as the configuration selects a single driver. Suggested-by:
Randy Dunlap <rdunlap@infradead.org> Acked-by:
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by:
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git://git.armlinux.org.uk/~rmk/linux-armGreg Kroah-Hartman authored
This merges from linux-arm at 860660fd ("ARM: 9055/1: mailbox: arm_mhuv2: make remove callback return void") into char-misc-next to get the amba fixes from Uwe. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'icc-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next Georgi writes: interconnect changes for 5.12 Here are the interconnect changes for the 5.12-rc1 merge window consisting of driver updates. Driver changes: - Refactoring and consolidation of drivers. - New driver for MSM8939 platforms. - New driver for SDX55 platforms. Signed-off-by:
Georgi Djakov <djakov@kernel.org> * tag 'icc-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: qcom: Add SDX55 interconnect provider driver dt-bindings: interconnect: Add Qualcomm SDX55 DT bindings interconnect: qcom: Add MSM8939 interconnect provider driver dt-bindings: interconnect: Add Qualcomm MSM8939 DT bindings dt-bindings: interconnect: single yaml file for RPM interconnect drivers interconnect: qcom: qcs404: use shared code interconnect: qcom: Consolidate interconnect RPM support
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- 04 Feb, 2021 26 commits
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Uwe Kleine-König authored
My build tests failed to catch that amba driver that would have needed adaption in commit 3fd269e7 ("amba: Make the remove callback return void"). Change the remove function to make the driver build again. Link: https://lore.kernel.org/r/20210202194308.jm66vblqjwr5wo6v@pengutronix.deReported-by:
kernel test robot <lkp@intel.com> Fixes: 3fd269e7 ("amba: Make the remove callback return void") Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk>
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Ricky Wu authored
Power down OCP for power consumption when no SD/MMC card is present Cc: stable@vger.kernel.org Signed-off-by:
Ricky Wu <ricky_wu@realtek.com> Link: https://lore.kernel.org/r/20210204083115.9471-1-ricky_wu@realtek.comSigned-off-by:
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Samuel Thibault authored
In case the serial port or cable got faulty, we may not be getting acknowledgements any more. The driver then currently waits for 4s to avoid jamming the device. This makes this delay configurable. Signed-off-by:
Samuel Thibault <samuel.thibault@ens-lyon.org> Link: https://lore.kernel.org/r/20210128180116.1848120-3-samuel.thibault@ens-lyon.orgSigned-off-by:
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Samuel Thibault authored
The parameters were advertised for the "soft" synth, but they are available for all synths. Signed-off-by:
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Ahmad Fatoum authored
The nvmem cell binding applies to all eeprom child nodes matching "^.*@[0-9a-f]+$" without taking a compatible into account. Linux drivers, like at24, are even more extensive and assume _all_ at24 eeprom child nodes to be nvmem cells since e888d445 ("nvmem: resolve cells from DT at registration time"). Since df5f3b6f ("dt-bindings: nvmem: stm32: new property for data access"), the additionalProperties: True means it's Ok to have other properties as long as they don't match "^.*@[0-9a-f]+$". The barebox bootloader extends the MTD partitions binding to EEPROM and can fix up following device tree node: &eeprom { partitions { compatible = "fixed-partitions"; }; }; This is allowed binding-wise, but drivers using nvmem_register() like at24 will fail to parse because the function expects all child nodes to have a reg property present. This results in the whole EEPROM driver probe failing despite the device tree being correct. Fix this by skipping nodes lacking a reg property instead of returning an error. This effectively makes the drivers adhere to the binding because all nodes with a unit address must have a reg property and vice versa. Fixes: e888d445 ("nvmem: resolve cells from DT at registration time"). Signed-off-by:
Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by:
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Nicolas Saenz Julienne authored
Firmware/co-processors might use reserved memory areas in order to pass data stemming from an nvmem device otherwise non accessible to Linux. For example an EEPROM memory only physically accessible to firmware, or data only accessible early at boot time. In order to expose this data to other drivers and user-space, the driver models the reserved memory area as an nvmem device. Tested-by:
Tim Gover <tim.gover@raspberrypi.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Nicolas Saenz Julienne authored
Firmware/co-processors might use reserved memory areas in order to pass data stemming from an nvmem device otherwise non accessible to Linux. For example an EEPROM memory only physically accessible to firmware, or data only accessible early at boot time. Introduce the dt-bindings to nvmem's rmem. Reviewed-by:
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Fabio Estevam authored
The retrieval of driver data via of_device_get_match_data() can make the code simpler. Use of_device_get_match_data() to simplify the code. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
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Dan Carpenter authored
This doesn't call of_node_put() on the error path so it leads to a memory leak. Fixes: 0749aa25 ("nvmem: core: fix regression in of_nvmem_cell_get()") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Yang Li authored
Fix the following coccicheck warning: ./drivers/misc/cxl/sysfs.c:181:48-53: WARNING: conversion to bool not needed here Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reviewed-by:
Andrew Donnellan <ajd@linux.ibm.com> Acked-by:
Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1611908705-98507-1-git-send-email-yang.lee@linux.alibaba.comSigned-off-by:
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Suzuki K Poulose authored
TRCSTALLCTLR register is only implemented if TRCIDR3.STALLCTL == 0b1 Make sure the driver touches the register only it is implemented. Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com Cc: stable@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-32-mathieu.poirier@linaro.orgSigned-off-by:
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Jonathan Zhou authored
v8.4 tracing extensions added support for trace filtering controlled by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2 tracing if we are running the kernel at EL2. Link: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Will Deacon <will@kernel.org> Reviewed-by:
Jonathan Zhou <jonathan.zhouwen@huawei.com> [ Move the trace filtering setup etm_init_arch_data() and clean ups] Signed-off-by:
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Jonathan Zhou authored
Add definitions for the Arm v8.4 SelfHosted trace extensions registers. [ split the register definitions to separate patch rename some of the symbols ] Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com Cc: Will Deacon <will@kernel.org> Acked-by:
Catalin Marinas <catalin.marinas@arm.com> Signed-off-by:
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Suzuki K Poulose authored
Document the bindings for ETMs with system register accesses. Link: https://lore.kernel.org/r/20210110224850.1880240-27-suzuki.poulose@arm.com Cc: devicetree@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Acked-by:
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Suzuki K Poulose authored
Add support for devices with system instruction access only. They don't have a memory mapped interface and thus are not AMBA devices. System register access is not permitted to TRCPDCR and thus skip access to them. Link: https://lore.kernel.org/r/20210110224850.1880240-26-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
As we are about to add support for system register based devices, we don't get an AMBA pid. So, the detection code could check the system registers running on the CPU to check for the architecture specific features. Thus we move the arch feature detection to run on the CPU. We cannot always read the PID from the HW, as the PID could be overridden by DT for broken devices. So, use the PID from AMBA layer if available. Link: https://lore.kernel.org/r/20210110224850.1880240-25-suzuki.poulose@arm.com Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: liuqi115@huawei.com Signed-off-by:
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Suzuki K Poulose authored
CoreSight ETM with system register access may not have a memory mapped i/o access. Refactor the ETM specific probing into a common routine to allow reusing the code for such ETMs. Link: https://lore.kernel.org/r/20210110224850.1880240-24-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
ETM v4.4 onwards adds support for system instruction access to the ETM. Detect the support on an ETM and switch to using the mode when available. Link: https://lore.kernel.org/r/20210110224850.1880240-23-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
As per the specification any update to the TRCPRGCTLR must be synchronized by a context synchronization event (in our case an explicist ISB) before the TRCSTATR is checked. Link: https://lore.kernel.org/r/20210110224850.1880240-22-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Expose the TRCDEVARCH register via the sysfs for component detection. Given that the TRCIDR1 may not completely identify the ETM component and instead need to use TRCDEVARCH, expose this via sysfs for tools to use it for identification. Link: https://lore.kernel.org/r/20210110224850.1880240-21-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
We have been using TRCIDR1 for detecting the ETM version. This is in preparation for the future IP support. Link: https://lore.kernel.org/r/20210110224850.1880240-20-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
In preparation to detect the support for system instruction support, move the detection of the device access to the target CPU. Link: https://lore.kernel.org/r/20210110224850.1880240-19-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Link: https://lore.kernel.org/r/20210110224850.1880240-18-suzuki.poulose@arm.comSigned-off-by:
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Suzuki K Poulose authored
etm4_get_access_type() calculates the exception level bits for use in address comparator registers. This is also used by the TRCVICTLR register by shifting to the required position. This patch cleans up the logic to make etm4_get_access_type() calculate a generic mask which can be used by all users by shifting to their field. No functional changes intended. Link: https://lore.kernel.org/r/20210110224850.1880240-17-suzuki.poulose@arm.comSigned-off-by:
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Suzuki K Poulose authored
We rely on the ETM architecture version to decide whether Secure EL2 is available on the CPU for excluding the level for address comparators and viewinst main control register. We must instead use the TRCDIDR3.EXLEVEL_S field to detect the supported levels. Link: https://lore.kernel.org/r/20210110224850.1880240-16-suzuki.poulose@arm.comSigned-off-by:
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Suzuki K Poulose authored
The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
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