- 20 Jul, 2016 16 commits
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David S. Miller authored
Vivien Didelot says: ==================== net: dsa: mv88e6xxx: Global2 cleanup and STP The Marvell switches registers are organized in distinct internal SMI devices, such as PHY, Port, Global 1 or Global 2 registers sets. Since not all chips support every registers sets or have slightly differences in them (such as old 88E6060 or new 88E6390 likely to be supported soon), make the setup code clearer now by removing a few family checks and adding flags to describe the Global 2 registers map. This patchset enables basic STP support and bridging on most chips when getting rid of a few inconsistencies in chip descriptions (patch 1) and add bridge Ageing Time support to DSA and the mv88e6xxx driver. Changes v2 -> v3: - rename mv88e6xxx_update_write to mv88e6xxx_update - set fastest ageing time in use in the chip for multiple bridges, tested with a few printk Changes v1 -> v2: - add a write helper for pointer-data Update registers - add ageing time support ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Implement the DSA driver function to configure the bridge ageing time. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Vivien Didelot authored
All Marvell switch chips from (88E6060 to 88E6390) have a ATU Control register containing bits 11:4 to configure an ATU Age Time quotient. However the coefficient used to calculate the ATU Age Time vary with the models. E.g. 88E6060, 88E6352 and 88E6390 use respectively 16, 15 and 3.75 seconds. Add a age_time_coeff to the info structure to handle this and a Global 1 helper to set the default age time of 5 minutes in the setup code. Signed-off-by:
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Vivien Didelot authored
Add a new function for DSA drivers to handle the switchdev SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME attribute. The ageing time is passed as milliseconds. Also because we can have multiple logical bridges on top of a physical switch and ageing time are switch-wide, call the driver function with the fastest ageing time in use on the chip instead of the requested one. Signed-off-by:
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Vivien Didelot authored
Add capability flags to describe the presence of Ingress Rate Limit unit registers and an helper function to clear it. In the meantime, fix a few harmless issues: - 6185 and 6095 don't have such registers (reserved) - the previous code didn't wait for the IRL operation to complete Signed-off-by:
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Vivien Didelot authored
Add flags and helpers to describe the presence of Priority Override Table (POT) related registers and simplify the setup of Global 2. Signed-off-by:
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Vivien Didelot authored
Add flags to describe the presence of Cross-chip Port VLAN Table (PVT) related registers and simplify the setup of Global 2. Signed-off-by:
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Vivien Didelot authored
Switches such as 88E6185 as 3 Switch MAC registers in Global 1. Newer chips such as 88E6352 have freed these registers in favor of an indirect access in a Switch MAC/WoL/WoF register in Global 2. Explicit this difference with G1 and G2 helpers and flags. Also, note that this indirect access is a single-register which doesn't require to wait for the operation to complete (like Switch MAC, Trunk Mapping, etc.), in contrary to multi-registers indirect accesses with several operations and a busy bit. Signed-off-by:
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Vivien Didelot authored
Some switches provide a Rsvd2CPU mechanism used to choose which of the 16 reserved multicast destination addresses matching 01:80:c2:00:00:0x should be considered as MGMT and thus forwarded to the CPU port. Other switches extend this mechanism to also configure as MGMT the additional 16 reserved multicast addresses matching 01:80:c2:00:00:2x. This mechanism is exposed via two registers in Global 2, and an Rsvd2CPU enable bit in the management register. Newer chip (such as 88E6390) has replaced these registers with a new indirect MGMT mechanism in Global 1. The patch adds two MV88E6XXX_FLAG_G2_MGMT_EN_{0,2}X flags to describe the presence of these Global 2 registers. If 88E6390 support is added, a MV88E6XXX_FLAG_G1_MGMT_CTRL flag will be needed to setup Rsvd2CPU. Note: all switches still support in parallel the ATU Load operation with an MGMT Entry State to forward such frames in a less convenient way. Signed-off-by: -
Vivien Didelot authored
The Trunk Mask and Trunk Mapping registers are two Global 2 indirect accesses to trunking configuration. Add helpers for these tables and simplify the Global 2 setup. Signed-off-by:
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Vivien Didelot authored
The Device Mapping register is an indirect table access. Provide helpers to access this table and explicit the checking of the new DSA_RTABLE_NONE routing table value. Signed-off-by:
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Vivien Didelot authored
Separate the setup of Global 1 and Global 2 internal SMI devices and add a flag to describe the presence of this second registers set. Also rearrange the G1 setup in the registers order. Signed-off-by:
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Vivien Didelot authored
All 88E6xxx Marvell switches (even the old not supported yet 88E6060) have at least an ATU, per-port STP states and VLAN map, to run basic switch functions such as Spanning Tree and port based VLANs. Get rid of the related MV88E6XXX_FLAG_{ATU,PORTSTATE,VLANTABLE} flags, as they are defaults to every chip. This enables STP on 6185 and removes many inconsistencies on others. Signed-off-by: -
Andrew Morton authored
kernel/trace/bpf_trace.c: In function 'bpf_event_output': kernel/trace/bpf_trace.c:312: error: unknown field 'next' specified in initializer kernel/trace/bpf_trace.c:312: warning: missing braces around initializer kernel/trace/bpf_trace.c:312: warning: (near initialization for 'raw.frag.<anonymous>') Fixes: 555c8a86 ("bpf: avoid stack copy and use skb ctx for event output") Acked-by:
Daniel Borkmann <daniel@iogearbox.net> Cc: Alexei Starovoitov <ast@kernel.org> Cc: David S. Miller <davem@davemloft.net> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Acked-by:
Alexei Starovoitov <ast@kernel.org> Signed-off-by:
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Andy Lutomirski authored
VLAN and MQ control was doing DMA from the stack. Fix it. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org> Signed-off-by:
Andy Lutomirski <luto@kernel.org> Acked-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
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Florian Fainelli authored
txr->dev_state was not consistently manipulated with the acquisition of the per-queue lock, after further inspection the lock does not seem necessary, either the value is read as BNXT_DEV_STATE_CLOSING or 0. Reported-by: coverity (CID 1339583) Fixes: c0c050c5 ("bnxt_en: New Broadcom ethernet driver.") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Acked-by:
Michael Chan <michael.chan@broadcom.com> Signed-off-by:
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- 19 Jul, 2016 21 commits
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David S. Miller authored
Shmulik Ladkani says: ==================== net: Consider fragmentation of udp tunneled skbs in 'ip_finish_output_gso' Currently IP fragmentation of GSO segments that exceed dst mtu is considered only in the ipv4 forwarding case. There are cases where GSO skbs that are bridged and then udp-tunneled may have gso_size exceeding the egress device mtu. It makes sense to fragment them, as in the non GSOed code path. The exact cases where this behavior is needed is described and addressed in the 2nd patch. ==================== Signed-off-by: -
Shmulik Ladkani authored
net: ip_finish_output_gso: If skb_gso_network_seglen exceeds MTU, allow segmentation for local udp tunneled skbs Given: - tap0 and vxlan0 are bridged - vxlan0 stacked on eth0, eth0 having small mtu (e.g. 1400) Assume GSO skbs arriving from tap0 having a gso_size as determined by user-provided virtio_net_hdr (e.g. 1460 corresponding to VM mtu of 1500). After encapsulation these skbs have skb_gso_network_seglen that exceed eth0's ip_skb_dst_mtu. These skbs are accidentally passed to ip_finish_output2 AS IS. Alas, each final segment (segmented either by validate_xmit_skb or by hardware UFO) would be larger than eth0 mtu. As a result, those above-mtu segments get dropped on certain networks. This behavior is not aligned with the NON-GSO case: Assume a non-gso 1500-sized IP packet arrives from tap0. After encapsulation, the vxlan datagram is fragmented normally at the ip_finish_output-->ip_fragment code path. The expected behavior for the GSO case would be segmenting the "gso-oversized" skb first, then fragmenting each segment according to dst mtu, and finally passing the resulting fragments to ip_finish_output2. 'ip_finish_output_gso' already supports this "Slowpath" behavior, according to the IPSKB_FRAG_SEGS flag, which is only set during ipv4 forwarding (not set in the bridged case). In order to support the bridged case, we'll mark skbs arriving from an ingress interface that get udp-encaspulated as "allowed to be fragmented", causing their network_seglen to be validated by 'ip_finish_output_gso' (and fragment if needed). Note the TUNNEL_DONT_FRAGMENT tun_flag is still honoured (both in the gso and non-gso cases), which serves users wishing to forbid fragmentation at the udp tunnel endpoint. Cc: Hannes Frederic Sowa <hannes@stressinduktion.org> Cc: Florian Westphal <fw@strlen.de> Signed-off-by:
Shmulik Ladkani <shmulik.ladkani@gmail.com> Acked-by:
Hannes Frederic Sowa <hannes@stressinduktion.org> Signed-off-by:
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Shmulik Ladkani authored
This flag indicates whether fragmentation of segments is allowed. Formerly this policy was hardcoded according to IPSKB_FORWARDED (set by either ip_forward or ipmr_forward). Cc: Hannes Frederic Sowa <hannes@stressinduktion.org> Cc: Florian Westphal <fw@strlen.de> Signed-off-by:
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David S. Miller authored
Michael Chan says: ==================== bnxt_en: Add support for NS2 Nitro. This series adds support for the embedded version of the ethernet controller (Nitro) in the North Star 2 SoC. There are a number of features not supported and a software workaround for a hardware rx bug is required for Nitro A0. Please review. ==================== Signed-off-by: -
Prashant Sreedharan authored
A bridge device in NS2 has the same device ID as the ethernet controller. Add check to avoid probing the bridge device. Signed-off-by:
Prashant Sreedharan <prashant.sreedharan@broadcom.com> Signed-off-by:
Vasundhara Volam <vasundhara-v.volam@broadcom.com> Signed-off-by:
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Prashant Sreedharan authored
Allocate special vnic for dropping packets not matching the RX filters. First vnic is for normal RX packets and the driver will drop all packets on the 2nd vnic. Signed-off-by:
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Prashant Sreedharan authored
Allocate napi for special vnic, packets arriving on this napi will simply be dropped and the buffers will be replenished back to the HW. Signed-off-by:
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Prashant Sreedharan authored
The hardware is unable to drop rx packets not matching the RX filters. To workaround it, we create a special VNIC and configure the hardware to direct all packets not matching the filters to it. We then setup the driver to drop packets received on this VNIC. This patch creates the infrastructure for this VNIC, reserves a completion ring, and rx rings. Only shared completion ring mode is supported. The next 2 patches add a NAPI to handle packets from this VNIC and the setup of the VNIC. Signed-off-by:
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Prashant Sreedharan authored
Nitro A0 has a hardware bug in the rx path. The workaround is to create a special COS context as a path for non-RSS (non-IP) packets. Without this workaround, the chip may stall when receiving RSS and non-RSS packets. Add infrastructure to allow 2 contexts (RSS and CoS) per VNIC. Allocate and configure the CoS context for Nitro A0. Signed-off-by:
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Prashant Sreedharan authored
Nitro is the embedded version of the ethernet controller in the North Star 2 SoC. Add basic code to recognize the chip ID and disable the features (ntuple, TPA, ring and port statistics) not supported on Nitro A0. Signed-off-by:
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David S. Miller authored
Charles-Antoine Couret says: ==================== Marvell phy: fiber interface configuration Another patchset to manage correctly the fiber link for some concerned Marvell's phy like 88E1512. This patchset fixed the commit log for the third and last commits and a comment in the first commit. ==================== Signed-off-by: -
Charles-Antoine Couret authored
These functions used standards registers in a different page for both interfaces: copper and fiber. Reviewed-by:
Charles-Antoine Couret <charles-antoine.couret@nexvision.fr> Signed-off-by:
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Charles-Antoine Couret authored
To be correctly initilized, the fiber interface needs to be configured via autonegociation registers which use some customs options or registers. Reviewed-by:
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Charles-Antoine Couret authored
Add support for the fiber receiver error counter in the statistics. Rename the current counter which is for copper errors to phy_receive_errors_copper, so it is easy to distinguish copper from fiber. Reviewed-by:
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Charles-Antoine Couret authored
For concerned phy, the fiber link is checked before the copper link. According to datasheet, the link which is up is enabled. If both links are down, copper link would be used. To detect fiber link status, we used the real time status because of troubles with the copper method. Tested with Marvell 88E1512. Reviewed-by:
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David S. Miller authored
Sergei Shtylyov says: ==================== Fix DMA channel misreporting for the Renesas Ethernet drivers Here's a set of 2 patches against DaveM's 'net.git' repo fixing up the DMA channel reporting by 'ifconfig'... ==================== Signed-off-by: -
Sergei Shtylyov authored
Currently 'ifconfig' for the Ethernet devices handled by this driver shows "DMA chan: ff" while the driver doesn't use any DMA channels. Not assigning a value to 'net_device::dma' causes 'ifconfig' to correctly not report a DMA channel. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Currently 'ifconfig' for the Ethernet devices handled by this driver shows "DMA chan: ff" while the driver doesn't use any DMA channels. Not assigning a value to 'net_device::dma' causes 'ifconfig' to correctly not report a DMA channel. Signed-off-by:
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Christophe Jaillet authored
In 'get_scq', 'dma_alloc_coherent' has been used to allocate some resources, so we need to free them using 'dma_free_coherent' instead of 'kfree'. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Christophe Jaillet authored
In 'cpmac_open', 'dma_alloc_coherent' has been used to allocate some resources, so we need to free them using 'dma_free_coherent' instead of 'kfree'. Also, we don't need to free these resources if the allocation has failed. So I have slighly modified the goto label in this case. Signed-off-by:
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Jason Wang authored
We should use kfree_skb() instead of kfree() to free an skb. Fixes: 362899b8 ("macvtap: switch to use skb array") Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Jason Wang <jasowang@redhat.com> Signed-off-by:
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- 18 Jul, 2016 3 commits
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Philippe Reynes authored
There are two generics functions phy_ethtool_{get|set}_link_ksettings, so we can use them instead of defining the same code in the driver. Signed-off-by:Philippe Reynes <tremyfr@gmail.com> Signed-off-by:
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Philippe Reynes authored
The private structure contain a pointer to phydev, but the structure net_device already contain such pointer. So we can remove the pointer phydev in the private structure, and update the driver to use the one contained in struct net_device. Signed-off-by:
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Philippe Reynes authored
There are two generics functions phy_ethtool_{get|set}_link_ksettings, so we can use them instead of defining the same code in the driver. There was a check on CAP_NET_ADMIN in bfin_mac_ethtool_setsettings, but this check is already done in dev_ethtool, so no need to repeat it before calling the generic function. Signed-off-by:
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