- 14 Oct, 2021 9 commits
-
-
Ville Syrjälä authored
Pull the convoluted loadgen calculation into a small helper. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-7-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
-
Ville Syrjälä authored
DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist, also the spec says to skip all loadgen stuff. The code was dead anyway since it wasn't actually writing the value anywhere. Signed-off-by:
-
Ville Syrjälä authored
Use <4 instead of <=3 as the terminating condition for the loops over the 4 lanes. Signed-off-by:
-
Ville Syrjälä authored
All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans fit into u8. Shrink the types accordingly. Signed-off-by: -
Ville Syrjälä authored
The struct itself already has sufficient namespace. No need to duplicate it in the members. Signed-off-by:
-
Jani Nikula authored
Now that intel_sideband.[ch] has been decluttered, it's pure lpt/wpt iosf sideband. Let's call it intel_sbi, following the function naming. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
-
Jani Nikula authored
The snb+ pcode mailbox code is not sideband, so split it out to a separate file. As can be seen from the #include changes, very few places use both sideband and pcode. Code movement only. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
-
Jani Nikula authored
For the time being, neither the power sequencer nor the backlight code properly support two eDP panels simultaneously. While the software states will be independent, the same sets of registers will be used for both eDP panels, clobbering the hardware state and leading to errors. Gracefully disable dual eDP until proper support has been added. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Acked-by:
Swati Sharma <swati2.sharma@intel.com> Signed-off-by:
-
Jani Nikula authored
The VLV/CHV sideband code is pretty distinct from the rest of the sideband code. Split it out to new vlv_sideband.[ch]. Pure code movement with relevant #include changes, and a tiny checkpatch fix on top. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
-
- 12 Oct, 2021 9 commits
-
-
Lucas De Marchi authored
Nothing from intel-mid.h and this is only available on x86, so remove it as we prepare support for other architectures. Signed-off-by:
-
Rodrigo Vivi authored
Need to resync drm-intel-next with TTM and PXP stuff from drm-intel-gt-next that is now in drm/drm-next. Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Dave Airlie authored
This just moves this code out of the i915_display.c into a new standalone file. Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
-
Dave Airlie authored
This moves this functionality out of intel_display.c to separate self-contained file. Signed-off-by:
-
Dave Airlie authored
This just pulls this out into a function so it can be moved to another file easier. Signed-off-by:
-
Dave Airlie authored
I want to refactor some stuff using this so make it shared. Signed-off-by:
-
Dave Airlie authored
Start to refactor more stuff out of intel_display.c. These fit better in this file. This moves the rps boosting code as well as this is the only user of it. Signed-off-by:
-
Jani Nikula authored
The 128b/132b channel coding link training uses more straightforward TX FFE preset values. Reuse voltage tries and max vswing for retry logic. The delays for 128b/132b are still all wrong, but this is regardless a step forward. v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper v3: - Rebase - Modify intel_dp_adjust_request_changed() and intel_dp_link_max_vswing_reached() to take 128b/132b into account. (Ville) v4: - Train request printing for TX FFE (Ville) - Log 8b/10b vs. 128b/132b (Ville) - Add helper for per-lane max vswing / tx ffe (Ville) - Name functions with tx_ffe/vswing instead of 128b132b/8b10b Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
-
Jani Nikula authored
Add per-lane abstraction for max vswing reached to make follow-up cleaner, as this one reverses the conditions. v2: both conditions need to be true, reverse (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
-
- 11 Oct, 2021 4 commits
-
-
Dave Airlie authored
Merge tag 'drm-intel-gt-next-2021-10-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - Add uAPI for using PXP protected objects Mesa changes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064 - Add PCI IDs and LMEM discovery/placement uAPI for DG1 Mesa changes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11584 - Disable engine bonding on Gen12+ except TGL, RKL and ADL-S Cross-subsystem Changes: - Merges 'tip/locking/wwmutex' branch (core kernel tip) - "mei: pxp: export pavp client to me client bus" Core Changes: - Update ttm_move_memcpy for async use (Thomas) Driver Changes: - Enable GuC submission by default on DG1 (Matt B) - Add PXP (Protected Xe Path) support for Gen12 integrated (Daniele, Sean, Anshuman) See "drm/i915/pxp: add PXP documentation" for details! - Remove force_probe protection for ADL-S (Raviteja) - Add base support for XeHP/XeHP SDV (Matt R, Stuart, Lucas) - Handle DRI_PRIME=1 on Intel igfx + Intel dgfx hybrid graphics setup (Tvrtko) - Use Transparent Hugepages when IOMMU is enabled (Tvrtko, Chris) - Implement LMEM backup and restore for suspend / resume (Thomas) - Report INSTDONE_GEOM values in error state for DG2 (Matt R) - Add DG2-specific shadow register table (Matt R) - Update Gen11/Gen12/XeHP shadow register tables (Matt R) - Maintain backward-compatible nested batch behavior on TGL+ (Matt R) - Add new LRI reg offsets for DG2 (Akeem) - Initialize unused MOCS entries to device specific values (Ayaz) - Track and use the correct UC MOCS index on Gen12 (Ayaz) - Add separate MOCS table for Gen12 devices other than TGL/RKL (Ayaz) - Simplify the locking and eliminate some RCU usage (Daniel) - Add some flushing for the 64K GTT path (Matt A) - Mark GPU wedging on driver unregister unrecoverable (Janusz) - Major rework in the GuC codebase, simplify locking and add docs (Matt B) - Add DG1 GuC/HuC firmwares (Daniele, Matt B) - Remember to call i915_sw_fence_fini on guc_state.blocked (Matt A) - Use "gt" forcewake domain name for error messages instead of "blitter" (Matt R) - Drop now duplicate LMEM uAPI RFC kerneldoc section (Daniel) - Fix early tracepoints for requests (Matt A) - Use locked access to ctx->engines in set_priority (Daniel) - Convert gen6/gen7/gen8 read operations to fwtable (Matt R) - Drop gen11/gen12 specific mmio write handlers (Matt R) - Drop gen11 specific mmio read handlers (Matt R) - Use designated initializers for init/exit table (Kees) - Fix syncmap memory leak (Matt B) - Add pretty printing for buddy allocator state debug (Matt A) - Fix potential error pointer dereference in pinned_context() (Dan) - Remove IS_ACTIVE macro (Lucas) - Static code checker fixes (Nathan) - Clean up disabled warnings (Nathan) - Increase timeout in i915_gem_contexts selftests 5x for GuC submission (Matt B) - Ensure wa_init_finish() is called for ctx workaround list (Matt R) - Initialize L3CC table in mocs init (Sreedhar, Ayaz, Ram) - Get PM ref before accessing HW register (Vinay) - Move __i915_gem_free_object to ttm_bo_destroy (Maarten) - Deduplicate frequency dump on debugfs (Lucas) - Make wa list per-gt (Venkata) - Do not define dummy vma in stack (Venkata) - Take pinning into account in __i915_gem_object_is_lmem (Matt B, Thomas) - Do not report currently active engine when describing objects (Tvrtko) - Fix pdfdocs build error by removing nested grid from GuC docs (Akira) - Remove false warning from the rps worker (Tejas) - Flush buffer pools on driver remove (Janusz) - Fix runtime pm handling in i915_gem_shrink (Maarten) - Rework TTM object initialization slightly (Thomas) - Use fixed offset for PTEs location (Michal Wa) - Verify result from CTB (de)register action and improve error messages (Michal Wa) - Fix bug in user proto-context creation that leaked contexts (Matt B) - Re-use Gen11 forcewake read functions on Gen12 (Matt R) - Make shadow tables range-based (Matt R) - Ditch the i915_gem_ww_ctx loop member (Thomas, Maarten) - Use NULL instead of 0 where appropriate (Ville) - Rename pci/debugfs functions to respect file prefix (Jani, Lucas) - Drop guc_communication_enabled (Daniele) - Selftest fixes (Thomas, Daniel, Matt A, Maarten) - Clean up inconsistent indenting (Colin) - Use direction definition DMA_BIDIRECTIONAL instead of PCI_DMA_BIDIRECTIONAL (Cai) - Add "intel_" as prefix in set_mocs_index() (Ayaz) From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YWAO80MB2eyToYoy@jlahtine-mobl.ger.corp.intel.comSigned-off-by:
-
git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Cross-subsystem Changes: - fbdev/efifb: Release PCI device's runtime PM ref during FB destr\ oy (Imre) i915 Core Driver Changes: - Only access SFC_DONE in media when not fused off for graphics 12 and newer. - Double Memory latency values from pcode for DG2 (Matt Roper) - ADL-S PCI ID update (Tejas) - New DG1 PCI ID (Jose) - Fix regression with uncore refactoring (Dave) i915 Display Changes: - ADL-P display (XE_LPD) fixes and updates (Ankit, Jani, Matt Roper, Anusham, Jose, Imre, Vandita) - DG2 display fixes (Ankit, Jani) - Expand PCH_CNP tweaked display workaround to all newer displays (Anshuman) - General display simplifications and clean-ups (Jani, Swati, Jose, Ville) - PSR Clean-ups, dropping support for BDW/HSD and enable PSR2 selective fetch by default (Jose, Gwan-gyeong) - Nuke ORIGIN_GTT (Jose) - Return proper DPRX link training result (Lee) - FBC related refactor and fixes (Ville) - Yet another attempt to solve the fast+narrow vs slow+wide eDP link training (Kai-Heng) - DP 2.0 preparation work (Jani) - Silence __iomem sparse warn (Ville) - Clean up DPLL stuff (Ville) - Fix various dp/edp max rates (Matt Atwood, Animesh, Jani) - Remove VBT ddi_port_info caching (Jani) - DSI driver improvements (Lee) - HDCP fixes (Juston) - Associate ACPI connector nodes with connector entries (Heikki) - Add support for out-of-bound hotplug events (Hans) - VESA vendor block and drm/i915 MSO use of it (Jani) - Fixes for bigjoiner (Ville) - Update memory bandwidth parameters (RK) - DMC related fixes (Chris, Jose) - HDR related fixes and improvements (Tejas) - g4x/vlv/chv CxSR/wm fixes/cleanups (Ville) - Use BIOS provided value for RKL Audio's HDA link (Kai-Heng) - Fix the dsc check while selecting min_cdclk (Vandita) - Split and constify vtable (Dave) - Add ww context to intel_dpt_pin (Maarten) - Fix bdb version check (Lukasz) - DP per-lane drive settings prep work and other DP fixes (Ville) Signed-off-by:
-
git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v5.16: UAPI Changes: - Allow empty drm leases for creating separate GEM namespaces. Cross-subsystem Changes: - Slightly rework dma_buf_poll. - Add dma_resv_for_each_fence_unlocked to iterate, and use it inside the lockless dma-resv functions. Core Changes: - Allow devm_drm_of_get_bridge to build without CONFIG_OF for compile testing. - Add more DP2 headers. - fix CONFIG_FB dependency in fb_helper. - Add DRM_FORMAT_R8 to drm_format_info, and helpers for RGB332 and RGB888. - Fix crash on a 0 or invalid EDID. Driver Changes: - Apply and revert DRM_MODESET_LOCK_ALL_BEGIN. - Add mode_valid to ti-sn65dsi86 bridge. - Support multiple syncobjs in v3d. - Add R8, RGB332 and RGB888 pixel formats to GUD. - Use devm_add_action_or_reset in dw-hdmi-cec. Signed-off-by:
-
Dave Airlie authored
Merge tag 'amd-drm-next-5.16-2021-10-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.16-2021-10-08: amdgpu: - gart BO pin count fix - RAS fixes - Misc display fixes - Misc code cleanups - Validate IP discovery table - IOMMU handling fixes for hotplug - Cyan Skillfish display support - DP 2.0 fixes - Covert vega and navi to IP discovery based asic enumeration - JPEG fixes - More FP cleanup for display - DCC fixes for DCN3.x - Initial USB4 DP tunnelling support - Aldebaran MCE support amdkfd: - Misc bug fixes - Misc code cleanups - RAS fixes x86/MCE: - Export symbol for use by GPU driver Signed-off-by:
-
- 08 Oct, 2021 11 commits
-
-
kernel test robot authored
Generated by: scripts/checkincludes.pl Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Lv Ruyi authored
Remove all but the first include of reg_helper.h and core_types.h from dcn201_clk_mgr.c. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Signed-off-by:
-
Guchun Chen authored
adev_to_drm is used everywhere, so improve recent changes when accessing drm_device pointer from amdgpu_device. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Alex Sierra authored
This fix the deadlock with the BO reservations during SVM_BO evictions while allocations in VRAM are concurrently performed. More specific, while the ttm waits for the fence to be signaled (ttm_bo_wait), it already has the BO reserved. In parallel, the restore worker might be running, prefetching memory to VRAM. This also requires to reserve the BO, but blocks the mmap semaphore first. The deadlock happens when the SVM_BO eviction worker kicks in and waits for the mmap semaphore held in restore worker. Preventing signal the fence back, causing the deadlock until the ttm times out. We don't need to hold the BO reservation anymore during validation and mapping. Now the physical addresses are taken from hmm_range_fault. We also take migrate_mutex to prevent range migration while validate_and_map update GPU page table. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
-
Wayne Lin authored
[Why & How] Got Werror when building with Clang-13: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:195:2: error: variable 'ts' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:200:9: note: uninitialized use occurs here return ts; ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:180:2: note: variable 'ts' is declared here enum dpia_set_config_ts ts; ^ 1 error generated. Fix it. Reported-by:Mike Lothian <mike@fireburn.co.uk> Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
-
Alex Deucher authored
Missing 4.1.2. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
-
Colin Ian King authored
The variable result is being initialized with a value that is never read, it is being updated immediately afterwards in both branches of an if statement. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
-
Alex Deucher authored
Was missed when converting the driver over to IP based initialization. Tested-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
-
Jani Nikula authored
Add a function for checking source MST support. Drop intel_dp->can_mst and use intel_dp->mst_mgr.cbs to indicate the same. It's the single point of truth without additional state variables. In code, "source support" is also self-documenting as opposed to the vague "can mst". Reviewed-by:
-
Jani Nikula authored
Limit the supported UHBR rates based on the repeater support, if there are repeaters. This should be done in DP helper level, but that requires an overhaul of the LTTPR handling, as the max rate is not enough to represent how 128b/132b rates may be masked along the way. Curiously, the spec says: * Shall be cleared to 00h when operating in 8b/10b Link Layer. * Each LTTPR on the way back to the DPTX shall clear the bits that do not correspond to the LTTPR's current bit rate. It's rather vague if we can reliably use the field at this time due to the wording "operating" and "current". But it would seem bizarre to have to wait until trying to operate a 128b/132b link layer at a certain bit rate to figure this out. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
-
git://linuxtv.org/pinchartl/mediaDave Airlie authored
R-Car DU improvements & enhancements to misc drivers Most notably, - Non-contiguous buffer import support for rcar-du - r8a779a0 support preparation for rcar-du - COMPILE_TEST fixes for omapdrm and sti Signed-off-by:
-
- 07 Oct, 2021 7 commits
-
-
Lucas De Marchi authored
When trying to bring IS_ACTIVE to linux/kconfig.h I thought it wouldn't provide much value just encapsulating it in a boolean context. So I also added the support for handling undefined macros as the IS_ENABLED() counterpart. However the feedback received from Masahiro Yamada was that it is too ugly, not providing much value. And just wrapping in a boolean context is too dumb - we could simply open code it. As detailed in commit babaab2f ("drm/i915: Encapsulate kconfig constant values inside boolean predicates"), the IS_ACTIVE macro was added to workaround a compilation warning. However after checking again our current uses of IS_ACTIVE it turned out there is only 1 case in which it triggers a warning in clang (due -Wconstant-logical-operand) and 2 in smatch. All the others can simply use the shorter version, without wrapping it in any macro. So here I'm dialing all the way back to simply removing the macro. That single case hit by clang can be changed to make the constant come first, so it doesn't think it's mask: - if (context && CONFIG_DRM_I915_FENCE_TIMEOUT) + if (CONFIG_DRM_I915_FENCE_TIMEOUT && context) As talked with Dan Carpenter, that logic will be added in smatch as well, so it will also stop warning about it. Signed-off-by:
Masahiro Yamada <masahiroy@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20211005171728.3147094-1-lucas.demarchi@intel.com
-
Jani Nikula authored
The UHBR check was using > instead of >=. Use the helper instead to avoid mistakes. Also always use the non-UHBR values for HDMI. v2: Use intel_crtc_has_dp_encoder() && intel_dp_is_uhbr() (Ville) Fixes: 2817efae ("drm/i915/dg2: add SNPS PHY translations for UHBR link rates") Reported-by:
-
Nirmoy Das authored
Unify BO evicting functionality for possible memory types in amdgpu_ttm.c. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
-
Zenghui Yu authored
As per the comment on top of acpi_evaluate_dsm(): | * Evaluate device's _DSM method with specified GUID, revision id and | * function number. Caller needs to free the returned object. We should free the returned object of acpi_evaluate_dsm() to avoid memory leakage. Otherwise the kmemleak splat will be triggered at boot time (if we compile kernel with CONFIG_DEBUG_TEST_DRIVER_REMOVE=y). Fixes: 8e55f99c ("drm/i915: Invoke another _DSM to enable MUX on HP Workstation laptops") Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
Zenghui Yu <yuzenghui@huawei.com> Signed-off-by:
-
Kieran Bingham authored
Extend the rcar_du_device_info structure and rcar_du_output enum to support DSI outputs and utilise these additions to provide support for the R8A779A0 V3U platform. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
-
Kieran Bingham authored
Not all platforms require both per-crtc IRQ and per-crtc clock management. In preparation for suppporting such platforms, split the feature macro to be able to specify both features independently. The other features are incremented accordingly, to keep the two crtc features adjacent. Reviewed-by:
Kieran Bingham <kieran.bingham@ideasonboard.com> Signed-off-by:
-
Kieran Bingham authored
The DIDSR fields named LDCS were incorrectly defined as LCDS. Both the Gen2 and Gen3 documentation refer to the fields as the "LVDS Dot Clock Select". Correct the definitions. Reviewed-by:
-
