- 04 Mar, 2022 4 commits
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Robin Chen authored
[Why] The deep sleep mode need to be disabled in some PSR scenario. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Robin Chen <robin.chen@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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George Shen authored
[Why/How] Refactor original w/a to unify naming and simplify logic. This also re-enables the code that was previously skipped due to the disabling of the previous workaround logic. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
George Shen <George.Shen@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] HW expects OPP to be configured before ODM is enabled. Failure to do so can cause errors. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Calculations differ with HostVM enabled/disabled, causing underflow in configs with high refresh displays + scaling due to lower available BW [HOW] Check riommu_active in order to pass correct HostVM enablement to DML Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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- 02 Mar, 2022 36 commits
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Weiguo Li authored
Remove the redundant null check since the caller ensures that 'ctx' is never NULL. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Weiguo Li <liwg06@foxmail.com> Signed-off-by:
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Alex Deucher authored
Leftover from bring up. Not used anymore. Acked-by:
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Alex Deucher authored
Leftover from bring up. Not used anymore. Acked-by:
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Alex Deucher authored
These were leftover from bring up and are no longer necessary. The information is available via the IP discovery table. Acked-by:
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Alex Deucher authored
Rather than checking the asic_type. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Dillon Varone authored
Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Danijel Slivka authored
structure changed in smc_fw_version >= 0x3A4900, "uint16_t VcnActivityPercentage" replaced with "uint16_t VcnUsagePercentage0" and "uint16_t VcnUsagePercentage1" Signed-off-by:Danijel Slivka <danijel.slivka@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Prike Liang authored
Enable gfxoff routine for GC 10.3.7. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Prike Liang authored
Enable gfx power gating for GC 10.3.7. Signed-off-by:
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Prike Liang authored
This will enable the following block clock gating. - MC - SDMA - HDP - ATHUB - IH - VCN/JPEG Signed-off-by:
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Prike Liang authored
Enable gfx cg gate/ungate control for GC 10.3.7. Signed-off-by:
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Qiang Yu authored
Regression has been reported that suspend/resume may hang with the previous vm ready check commit. So bring back the evicted list check as a temp fix. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1922 Fixes: c1a66c3b ("drm/amdgpu: check vm ready by amdgpu_vm->evicting flag") Reviewed-by:
Qiang Yu <qiang.yu@amd.com> Signed-off-by:
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Yifan Zha authored
[Why] As PSP needs to verify the signature, CAP firmware must be loaded first when PSP loads firmwares. Otherwise, when DFC feature is enabled, CP firmwares would be loaded failed. [ 1149.160480] [drm] MM table gpu addr = 0x800022f000, cpu addr = 00000000a62afcea. [ 1149.209874] [drm] failed to load ucode CP_CE(0x8) [ 1149.209878] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.215914] [drm] failed to load ucode CP_PFP(0x9) [ 1149.215917] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.221941] [drm] failed to load ucode CP_ME(0xA) [ 1149.221944] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.228082] [drm] failed to load ucode CP_MEC1(0xB) [ 1149.228085] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.234209] [drm] failed to load ucode CP_MEC2(0xD) [ 1149.234212] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.242379] [drm] failed to load ucode VCN(0x1C) [ 1149.242382] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [How] Move CAP UCODE ID to the beginning of AMDGPU_UCODE_ID enum list. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
This will allow to enable the tests only after latest fix after which the tests passed on my system. I tested on NV21 standalone and Vega 10 and Polaris as pair with DRI_PRIME. It's possible there might be still issues on ASICs i don't have at my posession but that that the point of enbling the tests finally - if other people during testing will encounter errors they will report and I will be able to fix. The releated merge request for enabling libdrm tests suite is in https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/227Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Protect with drm_dev_enter/exit Reviewed-by:
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Yifan Zhang authored
Use IP version rather than codename for noretry set. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Yifan Zhang authored
otherwise adev->ip_versions is still empty when amdgpu_gmc_noretry_set is called. Reviewed-by:
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yipechai authored
1. Define amdgpu_ras_block_late_fini_default in amdgpu_ras.c as .ras_fini common function, which is called when .ras_fini of ras block isn't initialized. 2. Remove the code of using amdgpu_ras_block_late_fini to initialize .ras_fini in ras blocks. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in mca ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in sdma ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in hdp ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in xgmi ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in umc ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in mmhub ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in gfx ras block. Signed-off-by:
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yipechai authored
centrally calls the .ras_fini function of all ras blocks. Signed-off-by:
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yipechai authored
1. Move the variables of ras block instance members from specific xxx_ras_fini to general ras_fini call. 2. Function calls inside the modules only use parameters passed from xxx_ras_fini instead of ras block instance members. Signed-off-by:
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yipechai authored
Modify .ras_fini function pointer parameter so that we can remove redundant intermediate calls in some ras blocks. Signed-off-by:
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Shah Dharati authored
[Why] PSR Power on/off is done in PSR. Add a dc_debug option and dmub setting to use PHY implementation of this instead. [How] Add a dc_debug option and dmub setting to use PHY FSM Power up/down for PSR. Co-authored-by:
Shah Dharati <dharati.shah@amd.com> Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
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Dillon Varone authored
[WHY?] Some projectors support frame alternate 3D modes at 120Hz, but DAL3 does not create timings. Most active DP to HDMI dongles do not translate infoframes properly to use HW packing stereo mode. [HOW?] Create frame alternate 3D timings for displays that support it. Disable HW packing 3D mode on DP active dongles. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Tom Rix authored
Clang static analysis reports this error amdgpu_debugfs.c:1690:9: warning: 1st function call argument is an uninitialized value tmp = krealloc_array(tmp, i + 1, ^~~~~~~~~~~~~~~~~~~~~~~~~~~ realloc uses tmp, so tmp can not be garbage. And the return needs to be checked. Fixes: 5ce5a584 ("drm/amdgpu: add debugfs for reset registers list") Reviewed-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Chris Park authored
[Why] HDMI Compliance requires VIC to be set to 0 on 2D mode if HDMI_VIC is present. [How] When VIC and HDMI_VIC is both present, reset VIC to 0. Reviewed-by:
Chris Park <Chris.Park@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] To align coding style for how we use this across DCN. The resource creation ones can remain static, however. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Hansen Dsouza authored
RDPCS programming is done in DMUB remove legacy invalid code Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Philip Yang authored
To remove duplicate code, unify event message format and simplify new event add in the following patches. Use KFD_SMI_EVENT_MSG_SIZE to define msg size, the same size will be used in user space to alloc the msg receive buffer. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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