- 12 Sep, 2022 18 commits
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Ashutosh Dixit authored
Perf limit reasons bit positions were off by one. Fixes: fa68bff7 ("drm/i915/gt: Add sysfs throttle frequency interfaces") Cc: stable@vger.kernel.org # v5.18+ Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Acked-by:
Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by:
Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908155821.1662110-1-ashutosh.dixit@intel.comSigned-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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Lucas De Marchi authored
This reverts commit 487970e8. Updated bspec and workaround database note Wa_1409120013 is not needed for DG2 (or any Xe_LPD) platform. Simply check by display version 12. v2: Simplify condition check to display version (Matt Roper) Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Umesh Nerlige Ramappa authored
The worker is canceled in gt_park path, but earlier it was assumed that gt_park path cannot sleep and the cancel is asynchronous. This caused a race with suspend flow where the worker runs after suspend and causes an unclaimed register access warning. Cancel the worker synchronously since the gt_park is indeed allowed to sleep. v2: Fix author name and sign-off mismatch Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4419 Fixes: 77cdd054 ("drm/i915/pmu: Connect engine busyness stats from GuC to pmu") Reviewed-by:
John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220827002135.139349-1-umesh.nerlige.ramappa@intel.comSigned-off-by:
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Tomas Winkler authored
GSC requires more operational memory than available on chip. Reserve 4M of LMEM for GSC operation. The memory is provided to the GSC as struct resource to the auxiliary data of the child device. Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Signed-off-by:
Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Alan Previn <alan.previn.teres.alexis@intel.com> Signed-off-by:
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Tomas Winkler authored
Add pxp mode devstate to debugfs to monitor pxp state machine progress. This is useful to debug issues in scenarios in which the pxp state needs to be re-initialized, like during power transitions such as suspend/resume. With this debugfs the state could be monitored to ensure that pxp is in the ready state. CC: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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Alexander Usyskin authored
The check that hardware and host ready bits are set after start is redundant and may fail and disable driver if there is back-to-back link reset issued right after start. This happens during pxp mode transitions when firmware undergo reset. Remove these checks to eliminate such failures. Signed-off-by:
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Vitaly Lubart authored
Added transition to PXP mode in resume flow. CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by:
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Tomas Winkler authored
1. Retrieve extended operational memory physical pointers from the auxiliary device info. 2. Setup memory registers. 3. Notify firmware that the memory is ready by sending the memory ready command. 4. Disable PXP device if GSC is not in PXP mode. CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
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Tomas Winkler authored
Add GSC memory ready command. The command indicates to the firmware that extend operation memory was setup and the firmware may enter PXP mode. CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
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Vitaly Lubart authored
Exported common mkhi definitions from bus-fixup.c into a separate header file mkhi.h for other driver usage. Signed-off-by:
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Alexander Usyskin authored
Parametrize operational timeouts in order to support slow firmware on some graphics devices. Signed-off-by:
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Alexander Usyskin authored
Wait for reset work to complete before initiating stop reset flow sequence. Signed-off-by:
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Tomas Winkler authored
A work-around for a HW issue in XEHPSDV that manifests itself when SW reads a gsc register when gsc is sending an interrupt. The work-around is to disable interrupts and to use polling instead. Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by:
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Alexander Usyskin authored
Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by:
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Alexander Usyskin authored
Add slow_firmware flag to the gsc device definition and pass it to mei auxiliary device, this instructs the driver to use longer operation timeouts. Signed-off-by:
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Tomas Winkler authored
Add slow_firmware flag to the mei auxiliary device info to inform the mei driver about slow underlying firmware. Such firmware will require to use larger operation timeouts. Signed-off-by:
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Tomas Winkler authored
struct mei_aux_device is an interface structure requires proper documenation. Signed-off-by:
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Vitaly Lubart authored
Some platforms require the host to poll on the GSC registers instead of relaying on the interrupts. For those platforms, irq initialization should be skipped Signed-off-by:
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- 08 Sep, 2022 2 commits
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Nirmoy Das authored
Fix regression introduced by commit: "drm/i915: Individualize fences before adding to dma_resv obj" which sets obj->read_domains to 0 for both read and write paths. Also set obj->write_domain to 0 on read path which was removed by the commit. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6639 Fixes: 420a07b8 ("drm/i915: Individualize fences before adding to dma_resv obj") Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com> Cc: <stable@vger.kernel.org> # v5.16+ Cc: Matthew Auld <matthew.auld@intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907172641.12555-1-nirmoy.das@intel.com
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Niranjana Vishwanathapura authored
So far, different views (normal, partial, rotated and remapped) into the same object are only supported for GGTT mappings. But with the upcoming VM_BIND feature, PPGTT will also use the partial view mapping. Hence rename ggtt_view to more generic gtt_view. Signed-off-by:
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Acked-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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- 07 Sep, 2022 2 commits
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John Harrison authored
With the move to un-versioned filenames, it becomes more difficult to know exactly what version of a given firmware is being used. So add the patch level version number to the debugfs output. Also, support matching by patch level when selecting code paths for firmware compatibility. While a patch level change cannot be backwards breaking, it is potentially possible that a new feature only works from a given patch level onwards (even though it was theoretically added in an earlier version that bumped the major or minor version). Signed-off-by:
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John Harrison authored
There was a misunderstanding in how firmware file compatibility should be managed within i915. This has been clarified as: i915 must support all existing firmware releases forever new minor firmware releases should replace prior versions only backwards compatibility breaking releases should be a new file This patch cleans up the single fallback file support that was added as a quick fix emergency effort. That is now removed in preference to supporting arbitrary numbers of firmware files per platform. The patch also adds support for having GuC firmware files that are named by major version only (because the major version indicates backwards breaking changes that affect the KMD) and for having HuC firmware files with no version number at all (because the KMD has no interface requirements with the HuC). For GuC, the driver will report via dmesg if the found file is older than expected. For HuC, the KMD will no longer require updating for any new HuC release so will not be able to report what the latest expected version is. Signed-off-by:
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- 06 Sep, 2022 2 commits
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Rodrigo Vivi authored
Specially in GT reset case this could be triggered and try to disable things that had never been enabled. Let's add some protection here. Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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Matthew Auld authored
Just move the HAS_FLAT_CCS() check into needs_ccs_pages. This also then fixes i915_ttm_memcpy_allowed() which was incorrectly reporting true on DG1, even though it doesn't have small-BAR or flat-CCS. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6605 Fixes: efeb3caf ("drm/i915/ttm: disallow CPU fallback mode for ccs pages") Signed-off-by:
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- 05 Sep, 2022 1 commit
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Nirmoy Das authored
On system suspend when system memory is low then i915_gem_obj_copy_ttm() could fail trying to backup a lmem obj. GEM_WARN_ON() is not enough, suspend shouldn't continue if i915_ttm_backup() throws an error. v2: Keep the fdo issue till we have a igt test(Matt). v3: Use %pe(Andrzej) References: https://gitlab.freedesktop.org/drm/intel/-/issues/6529Reviewed-by:
Chris P Wilson <chris.p.wilson@intel.com> Signed-off-by:
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- 01 Sep, 2022 1 commit
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Rodrigo Vivi authored
We need to inform PCODE of a desired ring frequencies so PCODE update the memory frequencies to us. rps->min_freq and rps->max_freq are the frequencies used in that request. However they were unset when SLPC was enabled and PCODE never updated the memory freq. v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right frequencies from the get_ia_constants instead of the fake init of rps' min and max. v3: don't forget the max <= min return v4: Move all the freq conversion to intel_rps.c. And the max <= min check to where it belongs. v5: (Ashutosh) Fix old comment s/50 HZ/50 MHz and add a doc explaining the "raw format" Fixes: 7ba79a67 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled") Cc: <stable@vger.kernel.org> # v5.15+ Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Tested-by:Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com> Signed-off-by:
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- 31 Aug, 2022 1 commit
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Rodrigo Vivi authored
Fix for intel_guc_slpc_set_min_freq() warn: inconsistent returns '&slpc->lock'. v2: Avoid with_intel_runtime_pm with the internal goto/return. (Ashutosh) Also standardize the 'ret' if this came from the efficient setup. And avoid the 'unlikely'. Fixes: 95ccf312 ("drm/i915/guc/slpc: Allow SLPC to use efficient frequency") Reported-by:kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
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- 30 Aug, 2022 3 commits
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Matt Roper authored
On client DG2 platforms, optimal performance is achieved with the hardware's default "age based" thread execution setting. However on ATS-M, switching this to "round robin after dependencies" provides better performance. We'll add a new "tuning" feature flag to the ATS-M device info to enable/disable this setting. Bspec: 68331 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220826212718.409948-1-matthew.d.roper@intel.com
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Matt Roper authored
This reverts commit ca692081. The intent of Wa_14015141709 was to inform us that userspace can no longer control object-level preemption as it has on past platforms (i.e., by twiddling register bit CS_CHICKEN1[0]). The description of the workaround in the spec wasn't terribly well-written, and when we requested clarification from the hardware teams we were told that on the kernel side we should also probably stop setting FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the hardware to honor the settings in per-context register CS_CHICKEN1. It turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a mistake; even though CS_CHICKEN1[0] is non-operational and useless to userspace, there are other bits in the register that do still work and might need to be adjusted by userspace in the future (e.g., to implement other workarounds that show up). If we don't set FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would not take effect. This miscommunication came to light because another workaround (Wa_16013994831) has now shown up that requires userspace to adjust the value of CS_CHICKEN[10] in certain circumstances. To ensure userspace's updates to this chicken bit are handled properly by the hardware, we need to make sure that FF_SLICE_CS_CHICKEN1[14] is once again set by the kernel. Signed-off-by:
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Andrzej Hajda authored
In case of Small BAR configurations stolen local memory can be unmappable. Since the test does not touch the memory, passing I915_BO_ALLOC_GPU_ONLY flag to i915_gem_object_create_region, will prevent -ENOSPC error from _i915_gem_object_stolen_init. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6565Signed-off-by:
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- 29 Aug, 2022 1 commit
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Joonas Lahtinen authored
Remove the module parameters for configuring GuC log size. We should instead rely on tuning the defaults to be usable for reporting bugs. v2: - Use correct 1M unit Fixes: 8ad0152a ("drm/i915/guc: Make GuC log sizes runtime configurable") Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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- 26 Aug, 2022 1 commit
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Matt Roper authored
Although register tuning settings are generally implemented via the workaround infrastructure, it turns out that the DRAW_WATERMARK register is not properly saved/restored by hardware around power events (i.e., RC6 entry) so updates to the value cannot be applied in the usual manner. New workaround Wa_16014892111 informs us that any tuning updates to this register must instead be applied via an INDIRECT_CTX batch buffer. This will ensure that the necessary value is re-applied when a context begins running, even if an RC6 entry had wiped the register back to hardware defaults since the last context ran. Fixes: 6dc85721 ("drm/i915/dg2: Add additional tuning settings") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6642Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220823202449.83727-1-matthew.d.roper@intel.com
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- 25 Aug, 2022 4 commits
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Juston Li authored
pxp will not start correctly until after mei_pxp bind completes and intel_pxp_init_hw() is called. Wait for the bind to complete before proceeding with startup. This fixes a race condition during bootup where we observed a small window for pxp commands to be sent, starting pxp before mei_pxp bind completed. Changes since v2: - wait for pxp_component to bind instead of returning -EAGAIN (Daniele) Changes since v1: - check pxp_component instead of pxp_component_added (Daniele) - pxp_component needs tee_mutex (Daniele) - return -EAGAIN so caller knows to retry (Daniele) Signed-off-by:
Juston Li <justonli@chromium.org> Reviewed-by:
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Matt Roper authored
Unlike the Xe_HP platforms, MTL only has a single CCS engine; the quad-based engine masking logic does not apply to this platform (or presumably any future platforms that only have 0 or 1 CCS). Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
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Matt Roper authored
Previously only dgfx platforms had a 4MB MMIO range, but starting with MTL we now use the larger range for all platforms. Bspec: 63834, 63830 Signed-off-by:
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Radhakrishna Sripada authored
Bit12 of the Forcewake request register should not be cleared post gen12. Do not touch this bit while clearing during fw domain reset. v2: Tweak the comment to drop older platforms(MattR) Bspec: 52542 Signed-off-by:
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- 24 Aug, 2022 2 commits
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Vinay Belgaumkar authored
Host Turbo operates at efficient frequency when GT is not idle unless the user or workload has forced it to a higher level. Replicate the same behavior in SLPC by allowing the algorithm to use efficient frequency. We had disabled it during boot due to concerns that it might break kernel ABI for min frequency. However, this is not the case since SLPC will still abide by the (min,max) range limits. With this change, min freq will be at efficient frequency level at init instead of fused min (RPn). If user chooses to reduce min freq below the efficient freq, we will turn off usage of efficient frequency and honor the user request. When a higher value is written, it will get toggled back again. The patch also corrects the register which needs to be read for obtaining the correct efficient frequency for Gen9+. We see much better perf numbers with benchmarks like glmark2 with efficient frequency usage enabled as expected. v2: Address review comments (Rodrigo) v3: with efficient frequency being dynamic, it is possible that the req frequency may go beyond max freq. This will cause SLPC selftests to fail. Add a FIXME there to start the test with [RPn, RP0] instead and restore it afterwards. BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/5468 Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by:
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Jani Nikula authored
Commit 368d179a ("drm/i915/guc: Add GuC <-> kernel time stamp translation information") added intel_device_info_print_runtime() in the time info dump for no obvious reason or explanation in the commit message. It only logs the rawclk freq. Remove it. Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Signed-off-by:
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- 20 Aug, 2022 1 commit
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Matthew Auld authored
This reverts commit 6a079903. Everything in CI using GuC is now timing out[1], and killing the machine with this change (perhaps a deadlock?). CI was recently on fire due to some changes coming in from -rc1, so likely the pre-merge CI results for this series were invalid? For now just revert, unless GuC experts already have a fix in mind. [1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html? Signed-off-by:
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- 18 Aug, 2022 1 commit
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Matthew Brost authored
Add a delay, configurable via debugfs (default 34ms), to disable scheduling of a context after the pin count goes to zero. Disable scheduling is a costly operation as it requires synchronizing with the GuC. So the idea is that a delay allows the user to resubmit something before doing this operation. This delay is only done if the context isn't closed and less than a given threshold (default is 3/4) of the guc_ids are in use. As temporary WA disable this feature for the selftests. Selftests are very timing sensitive and any change in timing can cause failure. A follow up patch will fixup the selftests to understand this delay. Alan Previn: Matt Brost first introduced this series back in Oct 2021. However no real world workload with measured performance impact was available to prove the intended results. Today, this series is being republished in response to a real world workload that benefited greatly from it along with measured performance improvement. Workload description: 36 containers were created on a DG2 device where each container was performing a combination of 720p 3d game rendering and 30fps video encoding. The workload density was configured in a way that guaranteed each container to ALWAYS be able to render and encode no less than 30fps with a predefined maximum render + encode latency time. That means the totality of all 36 containers and their workloads were not saturating the engines to their max (in order to maintain just enough headrooom to meet the min fps and max latencies of incoming container submissions). Problem statement: It was observed that the CPU core processing the i915 soft IRQ work was experiencing severe load. Using tracelogs and an instrumentation patch to count specific i915 IRQ events, it was confirmed that the majority of the CPU cycles were caused by the gen11_other_irq_handler() -> guc_irq_handler() code path. The vast majority of the cycles was determined to be processing a specific G2H IRQ: i.e. INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE. These IRQs are sent by GuC in response to i915 KMD sending H2G requests: INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET. Those H2G requests are sent whenever a context goes idle so that we can unpin the context from GuC. The high CPU utilization % symptom was limiting density scaling. Root Cause Analysis: Because the incoming execution buffers were spread across 36 different containers (each with multiple contexts) but the system in totality was NOT saturated to the max, it was assumed that each context was constantly idling between submissions. This was causing a thrashing of unpinning contexts from GuC at one moment, followed quickly by repinning them due to incoming workload the very next moment. These event-pairs were being triggered across multiple contexts per container, across all containers at the rate of > 30 times per sec per context. Metrics: When running this workload without this patch, we measured an average of ~69K INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE events every 10 seconds or ~10 million times over ~25+ mins. With this patch, the count reduced to ~480 every 10 seconds or about ~28K over ~10 mins. The improvement observed is ~99% for the average counts per 10 seconds. Signed-off-by:
Matthew Brost <matthew.brost@intel.com> Signed-off-by:
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