- 23 Nov, 2022 38 commits
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Aurabindo Pillai authored
[Why&How] If the timing generator isnt running, it does not make sense to trigger a sync on the corresponding OTG. Check this condition before starting. Otherwise, this will cause error like: *ERROR* GSL: Timeout on reset trigger! Fixes: dc55b106 ("drm/amd/display: Disable phantom OTG after enable for plane disable") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Paulo Miguel Almeida authored
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in struct GOP_VBIOS_CONTENT and refactor the rest of the code accordingly. Important to mention is that doing a build before/after this patch results in no functional binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by:
Paulo Miguel Almeida <paulo.miguel.almeida.rodenas@gmail.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 5aa66375. This causes a blank screen on boot on an Asus G513QY / 6800M laptop. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2259 Cc: Aric Cyr <Aric.Cyr@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Zhongwei Zhang <Zhongwei.Zhang@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Ren Zhijie authored
If CONFIG_DRM_AMDGPU=y and CONFIG_DRM_AMD_DC is not set, gcc complained about unused-function : drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1705:13: error: ‘amdgpu_discovery_set_sriov_display’ defined but not used [-Werror=unused-function] static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors To fix this error, use CONFIG_DRM_AMD_DC to wrap the definition of amdgpu_discovery_set_sriov_display(). Fixes: 25263da3 ("drm/amdgpu: rework SR-IOV virtual display handling") Signed-off-by:Ren Zhijie <renzhijie2@huawei.com> Signed-off-by:
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Luben Tuikov authored
Fix minmax warning by using min_t() macro and explicitly specifying the assignment type. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by:
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Stanley.Yang authored
[Why] [ 754.862560] refcount_t: underflow; use-after-free. [ 754.862898] Call Trace: [ 754.862903] <TASK> [ 754.862913] amdgpu_job_free_cb+0xc2/0xe1 [amdgpu] [ 754.863543] drm_sched_main.cold+0x34/0x39 [amd_sched] [How] The fw_fence may be not init, check whether dma_fence_init is performed before job free Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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ZhenGuo Yin authored
Fixes: f7ba887f ("drm/amdgpu: Adjust logic around GTT size (v3)") Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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Jane Jian authored
root cause that S2A need to use deduct offset flag. after setting this flag, vcn0 doorbell value works. so return it as before Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Acked-by:
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lyndonli authored
Update the SW CTF limit from existing register when there's a fan failure detected via SMU interrupt. Signed-off-by:
lyndonli <Lyndon.Li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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lyndonli authored
update driver if header for smu_13_0_7 Signed-off-by:
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Candice Li authored
Send message to SMU to update bad memory page and bad channel info. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: -Add configuration 2 for ABM 2.3/2.4. -Add margin for HUBP for SubVp + DRR. -Fix no display after resume from WB/CB. -Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K. -Lower watermarks for enter/enter+exit latency. -Update support types for DCN314 to include z8 only and z8_z10 only state. -Add new value for soc bounding box and dummy pstate. -Override fclk chang latency when calculating prefetch schedule for subvp with low uclk. -Add check for DET fetch latency for dcn32. -Add check if PSR enabled when entering MALL. -Use base MALL allocation size calculations off vewport height. -Add YCBCR2020 to CSC matrix. -Implement DP-Tx portion to interact with DPIA. -Add debug option for increasing phantom lines. -Fix phantom plane/stream retain after fail validation. -Fix display corruption with VSR enable. -Set valid divider value for virtual and FRL/DP2. -Add new num clk levels struct for max mclk index. -Fix check for phantom BPP. -Fix rotated cursor offset calculation. Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Reviewed-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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David Galiffi authored
[Why] Underflow is observed when cursor is still enabled when the cursor rectangle is outside the bounds of it's surface viewport. [How] Update parameters used to determine when cursor should be disabled. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Alvin Lee authored
[Description] Revert change since enabling SubVP on 8K60 single cable results in corruption Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Dillon Varone authored
[WHY?] When calculating watermark and dlg values, the max mclk level index and associated speed are needed to find the correlated dummy latency value. Currently the incorrect index is given due to a clock manager refactor. [HOW?] Use num_memclk_level from num_entries_per_clk struct for getting the correct max mem speed. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Taimur Hassan authored
[Why] Pixel rate divider values should never be set to N/A (0xF) as the K1/K2 field is only 1/2 bits wide. [How] Set valid divider values for virtual and FRL/DP2 cases. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Taimur Hassan <Syed.Hassan@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] Brief corruption is observed on hotplug/unplug with certain display configurations when VSR is enabled. [How] Work around the issue by avoiding 2to1 ODM when stream plane_count is 0. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Alvin Lee authored
[Description] - If we fail validation, we should retain the phantom stream/planes - Full updates assume that phantom pipes will be fully removed, but if validation fails we keep the phantom pipes - Therefore we have to retain the plane/stream if validation fails (since the refcount is decremented before validation, and the expectation is that it's fully freed when the old dc_state is released) Reviewed-by:
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Alvin Lee authored
[Description] - Add debug option for increasing number of phantom lines Reviewed-by:
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Mustapha Ghaddar authored
[WHY] To implement BW Allocation as per USB4 spec chapter 10.7 [HOW] Implement the DP-Tx portion of the logic to interact with DPIA Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Rodrigo Siqueira authored
When some of the IGT tests are executed in DCN31, it is possible to see multiple occurrences of this warning: WARNING: CPU: 9 PID: 3482 at drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dcn30/dcn30_dpp.c:154 dpp3_program_post_csc+0x196/0x220 [amdgpu] [..] PU: 9 PID: 3482 Comm: amd_hdr Tainted: G W 5.18.0+ #3 IP: 0010:dpp3_program_post_csc+0x196/0x220 [amdgpu] [..] all Trace: <TASK> dpp3_cnv_setup+0x5d9/0x5f0 [amdgpu] ? dcn20_blank_pixel_data+0x30a/0x330 [amdgpu] dcn20_program_pipe+0x259/0xb40 [amdgpu] ? offset_to_id+0x1b0/0x1c0 [amdgpu] dcn20_program_front_end_for_ctx+0x36a/0x450 [amdgpu] commit_planes_for_stream+0x8eb/0x13e0 [amdgpu] This commit fix the above issue by adding YCBCR2020 coefficients to the DPP Color Space Converter (CSC) matrix. Reviewed-by:
Nawwar Ali <nawwar.ali@amd.com> Acked-by:
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Dillon Varone authored
[WHY?] MALL allocation size depends on the viewport height, not the addressable vertical lines, which will not match when scaling. [HOW?] Base MALL allocation size calculations off viewport height. Reviewed-by:
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Alvin Lee authored
[Description] - When attempting to enter MALL SS when a PSR panel is connected, we have to check that the PSR panel has already entered PSR because the vsync interrupt call is per display index (can be called for the non-PSR panel first) - Also don't override link settings when programming phantom stream (main and phantom pipe share the same link) Reviewed-by:
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Dillon Varone authored
[WHY?] Some configurations are constructed with very marginal DET buffers relative to the worst possible time required to fetch a swath. [HOW?] Add a check to see that the DET buffer allocated for each pipe can hide the latency for all pipes to fetch at least one swath. Reviewed-by:
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Dillon Varone authored
[WHY?] Prefetch is not budgetting time for dummy pstate when using subvp and low uclk. [HOW?] Override fclk change latency to use dummy pstate latency when calculating prefetch schedule for subvp configs with low uclk. Reviewed-by:
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Dillon Varone authored
[Description] New values for soc bounding box and dummy pstate. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Even if we block Z9 based on crossover threshold it's possible to allow for Z8. [How] There's support for this on DCN314, so update the support types to include a z8 only and z8_z10 only state. Update the decide_zstate_support function to allow for specifying these modes based on the Z8 threshold. DCN31 has z-state disabled, but still update the legacy code to map z8_only = disallow and z10_z8_only = z10_only to keep the support the same. Reviewed-by:
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Nicholas Kazlauskas authored
[Why & How] Update from HW, need to lower watermarks for enter/enter+exit latency. Reviewed-by:
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Alvin Lee authored
[Description] - For SubVP, we cannot support HW cursor if it's greater than 64 x 64 x 4 bytes in size - However, on certain config changes (i.e. pixel format) we can exit SubVP (then change to HW cursor) then re-enter SubVP without changing back to SW cursor because there is no SetCursorAttributes call - To workaround this issue, limit the HW cursor size to be less than 64 x 64 x 4 bytes whenever the stream is >= 4K - Also ensure this W/A only affects DCN that supports SubVP Reviewed-by:
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Tsung-hua Lin authored
[why] First MST sideband message returns AUX_RET_ERROR_HPD_DISCON on certain intel platform. Aux transaction considered failure if HPD unexpected pulled low. The actual aux transaction success in such case, hence do not return error. [how] Not returning error when AUX_RET_ERROR_HPD_DISCON detected on the first sideband message. v2: squash in fix (Alex) Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
Tsung-hua Lin <Tsung-hua.Lin@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Add margin for HUBP "jitter" for SubVp + DRR case - Also do a min transition even if MPO is added on a non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR) Reviewed-by:
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Camille Cho authored
[Why & How] Add configuration 2 for ABM 2.3/2.4 to suit customer preferences, which is to lower the brightness curves in 80%-100% range compared to the existing default config 0. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
Camille Cho <Camille.Cho@amd.com> Tested-by:
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Lyude Paul authored
There's been a very long running bug that seems to have been neglected for a while, where amdgpu consistently triggers a KASAN error at start: BUG: KASAN: global-out-of-bounds in read_indirect_azalia_reg+0x1d4/0x2a0 [amdgpu] Read of size 4 at addr ffffffffc2274b28 by task modprobe/1889 After digging through amd's rather creative method for accessing registers, I eventually discovered the problem likely has to do with the fact that on my dce120 GPU there are supposedly 7 sets of audio registers. But we only define a register mapping for 6 sets. So, fix this and fix the KASAN warning finally. Signed-off-by:
Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Reviewed-by:
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Yang Yingliang authored
As comment of pci_get_domain_bus_and_slot() says, it returns a pci device with refcount increment, when finish using it, the caller must decrement the reference count by calling pci_dev_put(). So before returning from amdgpu_device_resume|suspend_display_audio(), pci_dev_put() is called to avoid refcount leak. Fixes: 3f12acc8 ("drm/amdgpu: put the audio codec into suspend state before gpu reset V3") Reviewed-by:
Yang Yingliang <yangyingliang@huawei.com> Signed-off-by:
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Alex Deucher authored
We can reuse the same buffers on resume. v2: squash in S4 fix from Shikai Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2213Reviewed-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Lyude Paul authored
Coverity noticed this one, so let's fix it. Fixes: 7cce4cd6 ("drm/amdgpu/mst: Stop ignoring error codes and deadlocking") Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Cc: stable@vger.kernel.org # v5.6+
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Jack Xiao authored
If mes enabled, reserve VM invalidation engine 5 for firmware. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Bob zhou authored
This patch is used to fix following compilation issue with legacy gcc error: ‘for’ loop initial declarations are only allowed in C99 mode for (int i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { Signed-off-by:Bob zhou <bobzhou2@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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- 22 Nov, 2022 2 commits
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
GVT Changes: - gvt-next stuff mostly with refactor for the new MDEV interface. i915 Changes: - PSR fixes and improvements (Jouni) - DP DSC fixes (Vinod, Jouni) - More general display cleanups (Jani) - More display collor management cleanup targetting degamma (Ville) - remove circ_buf.h includes (Jiri) - wait power off delay at driver remove to optimize probe (Jani) - More audio cleanup targeting the ELD precompute readout (Ville) - Enable DC power states on all eDP ports (Imre) - RPL-P stepping info (Matt Atwood) - MTL enabling patches (RK) - Removal of DG2 force_probe (Matt) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Y3f71obyEkImXoUF@intel.com
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2022-11-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Core Changes: - Backmerge of drm-next Driver Changes: - Restore probe_range behaviour for userptr (Matt A) - Fix use-after-free on lmem_userfault_list (Matt A) - Never purge busy TTM objects (Matt A) - Meteorlake enabling (Daniele, Badal, Daniele, Stuart, Aravind, Alan) - Demote GuC kernel contexts to normal priority (John) - Use RC6 residency types as arguments to residency functions (Ashutosh, Rodrigo, Jani) - Convert some legacy DRM debugging macros to new ones (Tvrtko) - Don't deadlock GuC busyness stats vs reset (John) - Remove excessive line feeds in GuC state dumps (John) - Use i915_sg_dma_sizes() for all backends (Matt A) - Prefer REG_FIELD_GET in intel_rps_get_cagf (Ashutosh, Rodrigo) - Use GEN12_RPSTAT register for GT freq (Don, Badal, Ashutosh) - Remove unwanted TTM ghost obj check (Matt A) - Update workaround documentation (Lucas) - Coding style and static checker fixes and cleanups (Jani, Umesh, Tvrtko, Lucas, Andrzej) - Selftest improvements (Chris, Daniele, Riana, Andrzej) Signed-off-by:
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