- 12 May, 2022 1 commit
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Vaishnav Achath authored
Currently devres managed removal of the spi_controller happens after removing the power domain of the host platform_device.While this does not affect the clean removal of the controller, but affects graceful removal of the child devices if the child device removal requires issuing commands over SPI. Eg. flash device being soft reset to 1S-1S-1S mode before removal so that on next probe operations in 1S-1S-1S mode is successful. Failure is seen when `rmmod spi-cadence-quadspi` is performed: root@j7-evm:~# rmmod spi_cadence_quadspi [ 49.230996] cadence-qspi 47050000.spi: QSPI is still busy after 500ms timeout. [ 49.238209] spi-nor spi1.0: operation failed with -110 [ 49.244457] spi-nor spi1.0: Software reset failed: -110 and on subsequent modprobe the OSPI flash probe fails as it is in 8D-8D-8D mode since the previous soft reset did not happen. root@j7-evm:~# modprobe spi_cadence_quadspi [ 73.253536] spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff [ 73.260476] spi-nor: probe of spi0.0 failed with error -2 This commit adds necessary changes to perform spi_unregister_master() in the host device remove() so that the child devices are gracefully removed before the power domain is removed. changes tested on J721E with mt35xu512aba flash. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220511115516.14894-1-vaishnav.a@ti.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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- 11 May, 2022 4 commits
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Mark Brown authored
Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com> Patrice Chotard <patrice.chotard@foss.st.com>: From: Patrice Chotard <patrice.chotard@foss.st.com> This series update flags management in the following cases: - In APM mode, don't take care of TCF and TEF flags - Always check TCF flag in stm32_qspi_wait_cmd() - Don't check BUSY flag when sending new command
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Patrice Chotard authored
Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment. Signed-off-by:
Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220511074644.558874-4-patrice.chotard@foss.st.comSigned-off-by:
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Patrice Chotard authored
Currently, SR_TCF flag is checked in case there is data, this criteria is not correct. SR_TCF flags is set when programmed number of bytes has been transferred to the memory device ("bytes" comprised command and data send to the SPI device). So even if there is no data, we must check SR_TCF flag. Signed-off-by: -
Patrice Chotard authored
In APM mode, TCF and TEF flags are not set. To avoid timeout in stm32_qspi_wait_cmd(), don't check if TCF/TEF are set. Signed-off-by:
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- 10 May, 2022 2 commits
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Ian Abbott authored
Remove a couple of unnecessary casts to `(void *)` when initializing the `.data` members in the device ID table. Signed-off-by:
Ian Abbott <abbotti@mev.co.uk> Link: https://lore.kernel.org/r/20220510115141.212779-3-abbotti@mev.co.ukSigned-off-by:
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Ian Abbott authored
Fix "WARNING: Missing a blank line after declarations" reported by checkpatch.pl. Signed-off-by:
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- 09 May, 2022 10 commits
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Marc Kleine-Budde authored
In mx51_ecspi_prepare_message() the MX51_ECSPI_CONFIG register is setup for the current spi_message. After writing the register, there is a delay to ensure that the changes hit the hardware. This patch checks if the register MX51_ECSPI_CONFIG actually needs to be changed. If the register content is unchanged the function is left early, skipping the write to the hardware and the delay. This leads to a small, but measurable performance increase. For a given workload with small transfers on an imx6 single core the CPU load decreases from 30% to ~27%. Signed-off-by:
Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220502175457.1977983-10-mkl@pengutronix.deSigned-off-by:
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Marc Kleine-Budde authored
The driver supports several modes, one of them is PIO/IRQ "spi_imx_pio_transfer()". The data is exchanged with the IP core using PIO, an IRQ is setup to signal empty/full FIFOs and the end of the transfer. The IRQ and scheduling overhead for short transfers is significant. Using polling instead of IRQs can be beneficial to reduce the overall CPU load, especially on small transfer workloads. On an imx6 single core, a given RX workload of the mcp251xfd driver results in 40% CPU load. Using polling mode reduces the CPU load to 30%. This patch adds PIO polling support to the driver. For transfers with a duration of less than 30 µs the polling mode instead of IRQ based PIO mode is used. 30 µs seems to be a good compromise, which is used the by the SPI drivers for the raspberry Pi (spi-bcm2835, spi-bcm2835), too. Co-developed-by:
David Jander <david@protonic.nl> Signed-off-by:
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Marc Kleine-Budde authored
There's no need to embed the struct spi_bitbang into our private data (struct spi_imx_data), the spi core is flexible enough, so that we only need a pointer to the allocated struct spi_controller. This is also a preparation patch to add PIO based polling support to the driver. Co-developed-by:
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Marc Kleine-Budde authored
With patch: | 8caab75f ("spi: Generalize SPI "master" to "controller"") the SPI "master" was generalized to "controller". This patch completed the conversion of the spi-imx driver by replacing the remaining occurrences of master to controller. Signed-off-by:
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Marc Kleine-Budde authored
This patch replaces an open coded swahw32s(). Signed-off-by:
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Marc Kleine-Budde authored
This patch fixes the following sparse warning by using a swab32s() instead of a cpu_to_be32(). The driver is used on little endian systems only and we really want to swap the bytes. | drivers/spi/spi-imx.c:305:29: warning: incorrect type in assignment (different base types) | drivers/spi/spi-imx.c:305:29: expected unsigned int val | drivers/spi/spi-imx.c:305:29: got restricted __be32 [usertype] | drivers/spi/spi-imx.c:361:21: warning: incorrect type in assignment (different base types) | drivers/spi/spi-imx.c:361:21: expected unsigned int [assigned] [usertype] val | drivers/spi/spi-imx.c:361:21: got restricted __be32 [usertype] Signed-off-by:
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Marc Kleine-Budde authored
This patch fixes the following checkpatch warning, by making val an "unsigned int". | WARNING: Prefer 'unsigned int' to bare use of 'unsigned' | + unsigned val = 0; Signed-off-by:
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Marc Kleine-Budde authored
This patch fixes the following checkpatch warning by removing the trailing backslash: | WARNING: Avoid unnecessary line continuations | + spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ Signed-off-by:
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Marc Kleine-Budde authored
This patch fixes the following and similar sparse warnings by adding the missing identifier names to the function definitions: | WARNING: function definition argument 'struct spi_imx_data *' should also have an identifier name | #68: FILE: drivers/spi/spi-imx.c:68: | + int (*prepare_message)(struct spi_imx_data *, struct spi_message *); Signed-off-by:
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Yang Yingliang authored
It will cause null-ptr-deref if platform_get_resource_byname() returns NULL, we need check the return value. Fixes: 858e26a5 ("spi: spi-fsl-qspi: Reduce devm_ioremap size to 4 times AHB buffer size") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220505093954.1285615-1-yangyingliang@huawei.comSigned-off-by:
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- 04 May, 2022 1 commit
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Andrea Zanotti authored
The module omap2-mcspi does not support the interword delay parameter present in the spi transfer. On one side, if the module is instructed to use the dma, this parameter is correctly ignored. However, without the usage of the dma, that parameter should be used. The patch introduce the handling of such delay in the omap2-mcspi module, using standard spi_delay struct. The patch has been tested using as benchmark a DM3730. The delay function used (spi_delay_exec) is already present in the kernel and it checks on its own the validity of the input, as such, no additional checks are present. The range of usage of the udelay function is incremented to 200 us, as the change from udelay to usleep_range introduces not neglectible delays. Signed-off-by:
Andrea Zanotti <andreazanottifo@gmail.com> Link: https://lore.kernel.org/r/20220502111300.24754-1-andreazanottifo@gmail.comSigned-off-by:
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- 03 May, 2022 3 commits
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Biju Das authored
Add RSPI binding documentation for Renesas RZ/G2UL SoC. RSPI block is identical to one found on RZ/A, so no driver changes are required. The fallback compatible string "renesas,rspi-rz" will be used on RZ/G2UL. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220501082150.24662-1-biju.das.jz@bp.renesas.comSigned-off-by:
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Dan Carpenter authored
Return -ENOMEM of there is a dma mapping error. Do not return success. Fixes: 764f1b74 ("spi: add driver for MTK SPI NAND Flash Interface") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/YmwjUcTKyQNrrn2g@kiliSigned-off-by:
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Ian Abbott authored
The Cadence QSPI compatible string required for the SoCFPGA platform changed from the default "cdns,qspi-nor" to "intel,socfpga-qspi" with the introduction of an additional quirk in commit 98d948eb ("spi: cadence-quadspi: fix write completion support"). However, that change did not preserve the previously used quirk for this platform. Reinstate the `CQSPI_DISABLE_DAC_MODE` quirk for the SoCFPGA platform. Fixes: 98d948eb ("spi: cadence-quadspi: fix write completion support") Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by:
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- 27 Apr, 2022 5 commits
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Chuanhong Guo authored
Add device-tree binding documentation for Mediatek SPI-NAND Flash Interface. Signed-off-by:
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Chuanhong Guo authored
This driver implements support for the SPI-NAND mode of MTK NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20220424032527.673605-3-gch981213@gmail.comSigned-off-by:
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Mark Brown authored
Mediatek ECC changes: * Also parse the default nand-ecc-engine property if available * Make mtk_ecc.c a separated module needed for SPI controller driver
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Chuanhong Guo authored
The recently added ECC engine support introduced a generic property named nand-ecc-engine for ecc engine phandle. This patch adds support for this new property. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220424032527.673605-4-gch981213@gmail.com
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Chuanhong Guo authored
this code will be used in mediatek snfi spi-mem controller with pipelined ECC engine. Signed-off-by:
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- 25 Apr, 2022 14 commits
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Mark Brown authored
Merge series from 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>: 1.Add support for using GPIOs as chip select lines on Ingenic SoCs. 2.Add support for probing the spi-ingenic driver on the JZ4775 SoC, the X1000 SoC, and the X2000 SoC. 3.Modify annotation texts to be more in line with the current state.
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Alexander Shiyan authored
Since version 5.13, the standard syscon bindings have been added to all clps711x DT nodes, so we can now use the more general syscon_regmap_lookup_by_phandle function to get the syscon pointer. Signed-off-by:
Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.kernel.org/r/20220420061038.22570-1-eagle.alexander923@gmail.comSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220420090452.2588930-1-chi.minghao@zte.com.cnSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Matthias Schiffer authored
With the removal of the incorrect logic of cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previously allowed 8-8-8 ops). Signed-off-by:
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220420155616.281730-2-matthias.schiffer@ew.tq-group.comSigned-off-by:
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Matthias Schiffer authored
As suggested, this removes the whole cqspi_set_protocol() function, as it is not actually needed: - Checks for unsupported operations are already handled by supports_op(), removing the need to distinguish DTR and non-DTR modes in the buswidth setup - supports_op() ensures that the DTR flags match for all relevant parts of an operation, so op->cmd.dtr can be used instead of copying the flag to the cqspi_flash_pdata - The logic in cqspi_set_protocol() is moved to cqspi_calc_rdreg() and cqspi_write_setup() (with a helper macro CQSPI_OP_WIDTH()) The helper macro checks nbytes instead of buswidth for 0, for consistency with supports_op() etc. Suggested-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Luca Ceresoli authored
The hardware (except for the ROCKCHIP_SPI_VER2_TYPE2 version) does not support active-high native chip selects. However if such a CS is configured the core does not error as it normally should, because the 'ctlr->use_gpio_descriptors = true' line in rockchip_spi_probe() makes the core set SPI_CS_HIGH in ctlr->mode_bits. In such a case the spi-rockchip driver operates normally but produces an active-low chip select signal without notice. There is no provision in the current core code to handle this situation. Fix by adding a check in the ctlr->setup function (similarly to what spi-atmel.c does). This cannot be done reading the SPI_CS_HIGH but in ctlr->mode_bits because that bit gets always set by the core for master mode (see above). Fixes: eb1262e3 ("spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods") Signed-off-by:
Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://lore.kernel.org/r/20220421213251.1077899-1-luca.ceresoli@bootlin.comSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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周琰杰 (Zhou Yanjie) authored
1.Since it would be dangerous to specify a newer SoC's compatible string as the fallback of an older SoC's compatible string, we add support for the "ingenic,jz4775-spi" compatible string in the driver. This will permit to support the JZ4775 by having: compatible = "ingenic,jz4775-spi"; Instead of doing: compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi"; 2.Add support for probing the spi-ingenic driver on the X1000 SoC from Ingenic. From the X1000 SoC onwards, the maximum frequency allowed by the SSI module of Ingenic SoCs has been changed from 54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info" to set different maximum frequency values. 3.Add support for probing the spi-ingenic driver on the X2000 SoC from Ingenic. The X2000 SoC has only one native chip select line, so "max_native_cs" is introduced in "jz_soc_info" to set different maximum number of native chip select lines. 4.Because of the introduction of support for the X-series SoCs, the current driver is not only applicable to the JZ-series SoCs, so the description texts has been modified to avoid misunderstanding. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
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