- 19 Feb, 2018 40 commits
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Rex Zhu authored
Add sub-queries for stable pstate shader/memory clock. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Chunming Zhou authored
missed in gmc9. v2: squash in build fix (Rex) Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
Add initial infrastructure for manual dpm control. Reviewed-by:
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Rex Zhu authored
when this bit was set on module load, driver will allow the user over/under gpu clock and voltage through sysfs. by default, this bit was not set. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
abbreviate variable name number_of_performance_levels to num_of_pl in struct phm_odn_clock_levels Reviewed-by:
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Rex Zhu authored
The additional output are: PSTATE_SCLK and PSTATE_MCLK value in MHz as: 300 MHz (PSTATE_SCLK) 300 MHz (PSTATE_MCLK) Reviewed-by:
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Rex Zhu authored
User can use to calculate profiling ratios when set UMD Pstate. Reviewed-by:
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Rex Zhu authored
v2: delete uncessary blank line. Add static const modifiers to an array Reviewed-by: -
Rex Zhu authored
when cat pp_power_profile_mode on Vega10 NUM MODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL 0 3D_FULL_SCREEN : 70 60 1 3 1 POWER_SAVING : 90 60 0 0 2 VIDEO*: 70 60 0 0 3 VR : 70 90 0 0 4 COMPUTER : 30 60 0 6 5 CUSTOM : 0 0 0 0 the result show all the profile mode we can support and custom mode. user can echo the num(0-4) to pp_power_profile_mode to select the profile mode or can echo "5 value value value value" to enter CUSTOM mode. the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL. Reviewed-by:
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Rex Zhu authored
Setup smio table(smio registers's address and voltage ID) for various voltage domain. Reviewed-by:
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Rex Zhu authored
Store the voltage regulator configuration so we can properly query the voltage Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
Store the voltage regulator configuration, so we can properly query the voltage. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
show mclk info as in MHz on Cz/St as 0: 333Mhz * 1: 800Mhz Signed-off-by:
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Christian König authored
rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by:
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Christian König authored
Makes more sense than tracing the kernel pointer. Signed-off-by:
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Christian König authored
Trace all allocated PASIDs. Signed-off-by:
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Christian König authored
Start to always allocate a pasid for each VM. v2: use dev_warn when we run out of PASIDs Signed-off-by:
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Christian König authored
Free up a pasid after all fences signaled. v2: also handle the case when we can't allocate a fence array. Signed-off-by:
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Christian König authored
This way we can better handle the differences for CPU based updates. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
And rename it to struct gmc_funcs. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Signed-off-by:
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Christian König authored
And rename it to amdgpu_gmc as well. Signed-off-by:
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Christian König authored
No AGP support for in this driver. Signed-off-by:
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Christian König authored
Print that extra information on GMC v8. Signed-off-by:
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Christian König authored
Print that extra information on GMC v7. Signed-off-by:
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Christian König authored
sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by:
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Samuel Li authored
To improve cpu read performance. This is implemented for APUs currently. v2: Adapt to change https://lists.freedesktop.org/archives/amd-gfx/2017-October/015174.html v3: Adapt to change "forward begin_cpu_access callback to drivers" v4: Instead of v3, reuse drm_gem dmabuf_ops here. Also some minor fixes as suggested. v5: only set dma_buf ops when it is valid (Samuel) Signed-off-by:
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Harry Wentland authored
VM support is only available for CZ and newer APUs. Trying to enable it for dGPU will blow up in DC. v2: Don't enable gpu_vm_support for Raven yet since it leads to a black screen. Need to debug this further before enabling. Change-Id: Ibe467c36affe2e7a7ee740c8d4f73027ca807178 Signed-off-by:Harry Wentland <harry.wentland@amd.com> Suggested-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Alex Deucher authored
Check if DC is enabled before allowing scanout buffers to be pinned in system memory. Reviewed-by:
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Christian König authored
On CZ and newer APUs we can pin the fb into GART as well as VRAM. v2: Don't enable gpu_vm_support for Raven yet since it leads to a black screen. Need to debug this further before enabling. Signed-off-by: -
Yong Zhao authored
The new register settings are needed to fix a tlb invalidation issue when MMHUB power gating is turned on for Raven. Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Acked-by:
Eric Huang <JinhuiEric.Huang@amd.com> Reviewed-by:
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Krunoslav Kovac authored
We assume FP16 1.0 frame buffer value maps to 80 nits. DC changes are to make this configurable. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Bernstein authored
Update dcn10_init_hw such that initialization of relevant HW blocks for Maximus FPGA are also initialized (and not skipped). Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Leo (Sunpeng) Li authored
Implement the timing generator hooks for configure_crc and get_crc. Also implement is_tg_enabled, as configure_crc uses it. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
Add interfaces in DC for per CRTC CRC configuration and fetching. Also implement amdgpu_dm functions to hook onto DRM. Signed-off-by:
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Eric Bernstein authored
Cleanup to remove unused register definition from hw sequencer header file since implementation moved from hw sequencer to dchubub file. Signed-off-by:
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Yongqiang Sun authored
No need to use loop find opp, use opp in stream_res. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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