- 04 Mar, 2022 20 commits
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Christian König authored
We now have standard macros for that. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Instead of providing the ib index provide the job and ib pointers directly to the patch and parse functions for UVD and VCE. Also move the set/get functions for IB values to the IB declerations. Signed-off-by:
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Christian König authored
No function change, just move a bunch of definitions from amdgpu.h into separate header files. Signed-off-by:
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Jingwen Chen authored
[Why] after the reset domain introduced, the sched.ready will be init after hw_init, which will overwrite the setup in vcn hw_init, and lead to vcn ib test fail. [How] set disabled vcn to no_scheduler Fixes: 5fd8518d ("drm/amdgpu: Move scheduler init to after XGMI is ready") Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by:
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Christian König authored
Since we removed the context lock we need to make sure that not two threads are trying to install an entity at the same time. Signed-off-by:
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Yifan Zhang authored
This patch implements get_atc_vmid_pasid_mapping_info for gfx10.3 Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Yifan Zhang authored
Fix the NULL point issue: [ 3076.255609] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 3076.255624] #PF: supervisor instruction fetch in kernel mode [ 3076.255637] #PF: error_code(0x0010) - not-present page [ 3076.255649] PGD 0 P4D 0 [ 3076.255660] Oops: 0010 [#1] SMP NOPTI [ 3076.255669] CPU: 20 PID: 2415 Comm: kfdtest Tainted: G W OE 5.11.0-41-generic #45~20.04.1-Ubuntu [ 3076.255691] Hardware name: AMD Splinter/Splinter-RPL, BIOS VS2326337N.FD 02/07/2022 [ 3076.255706] RIP: 0010:0x0 [ 3076.255718] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [ 3076.255732] RSP: 0018:ffffb64283e3fc10 EFLAGS: 00010297 [ 3076.255744] RAX: 0000000000000000 RBX: 0000000000000008 RCX: 0000000000000027 [ 3076.255759] RDX: ffffb64283e3fc1e RSI: 0000000000000008 RDI: ffff8c7a87f60000 [ 3076.255776] RBP: ffffb64283e3fc78 R08: ffff8c7d88518ac0 R09: ffffb64283e3fa60 [ 3076.255791] R10: 0000000000000001 R11: 0000000000000001 R12: 000000000000000f [ 3076.255805] R13: ffff8c7bdcea5800 R14: ffff8c7a9f3f3000 R15: ffff8c7a8696bc00 [ 3076.255820] FS: 0000000000000000(0000) GS:ffff8c7d88500000(0000) knlGS:0000000000000000 [ 3076.255839] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3076.255851] CR2: ffffffffffffffd6 CR3: 0000000109e3c000 CR4: 0000000000750ee0 [ 3076.255866] PKRU: 55555554 [ 3076.255873] Call Trace: [ 3076.255884] dbgdev_wave_reset_wavefronts+0x72/0x160 [amdgpu] [ 3076.256025] process_termination_cpsch.cold+0x26/0x2f [amdgpu] [ 3076.256182] ? ktime_get_mono_fast_ns+0x4e/0xa0 [ 3076.256196] kfd_process_dequeue_from_all_devices+0x49/0x70 [amdgpu] [ 3076.256328] kfd_process_notifier_release+0x187/0x2b0 [amdgpu] [ 3076.256451] ? mn_itree_inv_end+0xdc/0x110 [ 3076.256463] __mmu_notifier_release+0x74/0x1f0 [ 3076.256474] exit_mmap+0x170/0x200 [ 3076.256484] ? __handle_mm_fault+0x677/0x920 [ 3076.256496] ? _cond_resched+0x19/0x30 [ 3076.256507] mmput+0x5d/0x130 [ 3076.256518] do_exit+0x332/0xaf0 [ 3076.256526] ? handle_mm_fault+0xd7/0x2b0 [ 3076.256537] do_group_exit+0x43/0xa0 [ 3076.256548] __x64_sys_exit_group+0x18/0x20 [ 3076.256559] do_syscall_64+0x38/0x90 [ 3076.256569] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by:
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Ruijing Dong authored
vcn fwlog is for debugging purpose only, by default, it is disabled. Signed-off-by:
Ruijing Dong <ruijing.dong@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Ruijing Dong authored
Add fw log in fw shared data structure. Reviewed-by:
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David Yu authored
Add DFC CAP support for aldebaran Initialize cap microcode in psp_init_sriov_microcode, the ta microcode will be initialized in psp_vxx_init_microcode Signed-off-by:
David Yu <David.Yu@amd.com> Reviewed-by:
Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
Aldebaran has 48-bit physical address support Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Lijo Lazar authored
Use IP version and refactor reset logic to apply to a list of devices. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Aric Cyr authored
drm/amd/display: 3.2.175 This version brings along following fixes: - Remove invalid RDPCS Programming in DAL - Make functional resource functions non-static - Reset VIC if HDMI_VIC is present - Add frame alternate 3D & restrict HW packed on dongles - Reg to turn on/off PSR Power seq in FSM - Modify plane removal sequence to avoid hangs - Pass HostVM enable flag into DCN3.1 DML - DC Validation failures - Program OPP before ODM - Refactor fixed VS w/a for PHY tests - Pass deep sleep disabled allow info to dmub fw - Refine the EDID override - [FW Promotion] Release 0.0.106.0 - Add verify_link_cap back for hdmi Acked-by:Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Charlene Liu authored
[why] hdmi specific: add verify link cap after retrive link cap. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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jinzh authored
[Why] We already get the SBIOS EDID via ACPI on KMD, but after that, we just use the monitor EDID to set it HDR caps [How] Make the SBIOS EDID override to read_edid() That can change the read EDID caps from the right EDID Reviewed-by:
jinzh <jinzh@github.amd.com> Tested-by:
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Robin Chen authored
[Why] The deep sleep mode need to be disabled in some PSR scenario. Reviewed-by:
Robin Chen <robin.chen@amd.com> Tested-by:
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George Shen authored
[Why/How] Refactor original w/a to unify naming and simplify logic. This also re-enables the code that was previously skipped due to the disabling of the previous workaround logic. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
George Shen <George.Shen@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] HW expects OPP to be configured before ODM is enabled. Failure to do so can cause errors. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Calculations differ with HostVM enabled/disabled, causing underflow in configs with high refresh displays + scaling due to lower available BW [HOW] Check riommu_active in order to pass correct HostVM enablement to DML Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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- 02 Mar, 2022 20 commits
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Weiguo Li authored
Remove the redundant null check since the caller ensures that 'ctx' is never NULL. Reviewed-by:
Weiguo Li <liwg06@foxmail.com> Signed-off-by:
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Alex Deucher authored
Leftover from bring up. Not used anymore. Acked-by:
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Alex Deucher authored
Leftover from bring up. Not used anymore. Acked-by:
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Alex Deucher authored
These were leftover from bring up and are no longer necessary. The information is available via the IP discovery table. Acked-by:
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Alex Deucher authored
Rather than checking the asic_type. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Dillon Varone authored
Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Danijel Slivka authored
structure changed in smc_fw_version >= 0x3A4900, "uint16_t VcnActivityPercentage" replaced with "uint16_t VcnUsagePercentage0" and "uint16_t VcnUsagePercentage1" Signed-off-by:Danijel Slivka <danijel.slivka@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Prike Liang authored
Enable gfxoff routine for GC 10.3.7. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Prike Liang authored
Enable gfx power gating for GC 10.3.7. Signed-off-by:
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Prike Liang authored
This will enable the following block clock gating. - MC - SDMA - HDP - ATHUB - IH - VCN/JPEG Signed-off-by:
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Prike Liang authored
Enable gfx cg gate/ungate control for GC 10.3.7. Signed-off-by:
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Qiang Yu authored
Regression has been reported that suspend/resume may hang with the previous vm ready check commit. So bring back the evicted list check as a temp fix. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1922 Fixes: c1a66c3b ("drm/amdgpu: check vm ready by amdgpu_vm->evicting flag") Reviewed-by:
Qiang Yu <qiang.yu@amd.com> Signed-off-by:
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Yifan Zha authored
[Why] As PSP needs to verify the signature, CAP firmware must be loaded first when PSP loads firmwares. Otherwise, when DFC feature is enabled, CP firmwares would be loaded failed. [ 1149.160480] [drm] MM table gpu addr = 0x800022f000, cpu addr = 00000000a62afcea. [ 1149.209874] [drm] failed to load ucode CP_CE(0x8) [ 1149.209878] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.215914] [drm] failed to load ucode CP_PFP(0x9) [ 1149.215917] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.221941] [drm] failed to load ucode CP_ME(0xA) [ 1149.221944] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.228082] [drm] failed to load ucode CP_MEC1(0xB) [ 1149.228085] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.234209] [drm] failed to load ucode CP_MEC2(0xD) [ 1149.234212] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.242379] [drm] failed to load ucode VCN(0x1C) [ 1149.242382] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [How] Move CAP UCODE ID to the beginning of AMDGPU_UCODE_ID enum list. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
This will allow to enable the tests only after latest fix after which the tests passed on my system. I tested on NV21 standalone and Vega 10 and Polaris as pair with DRI_PRIME. It's possible there might be still issues on ASICs i don't have at my posession but that that the point of enbling the tests finally - if other people during testing will encounter errors they will report and I will be able to fix. The releated merge request for enabling libdrm tests suite is in https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/227Signed-off-by:
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Andrey Grodzovsky authored
Protect with drm_dev_enter/exit Reviewed-by:
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Yifan Zhang authored
Use IP version rather than codename for noretry set. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Yifan Zhang authored
otherwise adev->ip_versions is still empty when amdgpu_gmc_noretry_set is called. Reviewed-by:
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yipechai authored
1. Define amdgpu_ras_block_late_fini_default in amdgpu_ras.c as .ras_fini common function, which is called when .ras_fini of ras block isn't initialized. 2. Remove the code of using amdgpu_ras_block_late_fini to initialize .ras_fini in ras blocks. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in mca ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of amdgpu_ras_block_late_fini in sdma ras block. Signed-off-by:
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