- 13 Dec, 2021 20 commits
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Lang Yu authored
We found some headaches on ASICs don't need that, so remove that for them. Suggested-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
Kevin Wang <kevinyang.wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lang Yu authored
Currently, we don't find some neccesities to power on/off SDMA in SMU hw_init/fini(). It makes more sense in SDMA hw_init/fini(). Signed-off-by:
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Felix Kuehling authored
Hawaii support is mostly untested these days. ROCm user mode also depends on custom firmware for AQL packet processing, that was never pushed upstream due to quality regressions in graphics driver testing. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Felix Kuehling authored
If an existing SVM range overlaps an svm_range_set_attr call, we would normally split it in order to update only the overlapping part. However, if the attributes of the existing range would not be changed splitting it is unnecessary. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Felix Kuehling authored
The existing function doesn't compare the access bitmaps and flags. This can result in failure to update those attributes in existing ranges when all other attributes remained unchanged. Because the access and flags attributes modify only some bits in the respective bitmaps, we cannot compare them directly. Instead we need to check whether applying the attributes to a particular range would change the bitmaps. A PREFETCH_LOC attribute must always trigger a migration, even if the attribute value remains unchanged. E.g. if some pages were migrated due to a CPU page fault, a prefetch must still be executed to migrate pages back to VRAM. Signed-off-by:
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Felix Kuehling authored
Add null-pointer check after the last svm_range_new call. This was originally reported by Zhou Qingyang <zhou1615@umn.edu> based on a static analyzer. To avoid duplicating the unwinding code from svm_range_handle_overlap, I merged the two functions into one. Signed-off-by:
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Philip Yang authored
Remove not unique timestamp WARNING as same timestamp interrupt happens on some chips, Drain fault need to wait for the processed_timestamp to be truly greater than the checkpoint or the ring to be empty to be sure no stale faults are handled. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1818Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Isabella Basso authored
This fixes the warning below by changing the prototype to a location that's actually included by the .c files that call amdgpu_kms_compat_ioctl: warning: no previous prototype for ‘amdgpu_kms_compat_ioctl’ [-Wmissing-prototypes] 37 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | ^~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by:Isabella Basso <isabbasso@riseup.net> Signed-off-by:
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Isabella Basso authored
This fixes warnings caused by global functions lacking prototypes:, such as: warning: no previous prototype for 'dcn303_hw_sequencer_construct' [-Wmissing-prototypes] 12 | void dcn303_hw_sequencer_construct(struct dc *dc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... warning: no previous prototype for ‘amdgpu_has_atpx’ [-Wmissing-prototypes] 76 | bool amdgpu_has_atpx(void) { | ^~~~~~~~~~~~~~~ Reviewed-by:Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Isabella Basso authored
This turns previously global functions into static, thus removing compile-time warnings such as: warning: no previous prototype for 'pm_set_resources_vi' [-Wmissing-prototypes] 113 | int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer, | ^~~~~~~~~~~~~~~~~~~ Signed-off-by: -
Isabella Basso authored
This turns previously global functions into static, thus removing compile-time warnings such as: warning: no previous prototype for 'amdgpu_vkms_output_init' [-Wmissing-prototypes] 399 | int amdgpu_vkms_output_init(struct drm_device *dev, | ^~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: -
Isabella Basso authored
This fixes various warnings relating to erroneous docstring syntax, of which some are listed below: warning: Function parameter or member 'adev' not described in 'amdgpu_atomfirmware_ras_rom_addr' ... warning: expecting prototype for amdgpu_atpx_validate_functions(). Prototype was for amdgpu_atpx_validate() instead ... warning: Excess function parameter 'mem' description in 'amdgpu_preempt_mgr_new' ... warning: Cannot understand * @kfd_get_cu_occupancy - Collect number of waves in-flight on this device ... warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Signed-off-by:
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Isabella Basso authored
Silences 166 compile-time warnings like: warning: 'UVD0_BASE' defined but not used [-Wunused-const-variable=] 129 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, | ^~~~~~~~~ warning: 'UMC0_BASE' defined but not used [-Wunused-const-variable=] 123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } }, | ^~~~~~~~~ Signed-off-by: -
Zhigang Luo authored
For the ASIC has big FB, it need more time to clear FB during reset. This change extended SRIOV VF waiting reset completion timeout from 5s to 10s. Signed-off-by:
Zhigang Luo <zhigang.luo@amd.com> Acked-by:
Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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Zhigang Luo authored
For SRIOV VF, the XGMI topology was not recovered after reset. This change added code to SRIOV VF reset function to update XGMI topology for SRIOV VF after reset. Signed-off-by:
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Zhigang Luo authored
For SRIOV VF, XGMI was not initialized in PSP during recover. This change added PSP XGMI initialization for SRIOV VF during recover. Signed-off-by:
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Zhigang Luo authored
On SRIOV, host driver can support FLR(function level reset) on individual VF within the hive which might bring the individual device back to normal without the necessary to execute the hive reset. If the FLR failed , host driver will trigger the hive reset, each guest VF will get reset notification before the real hive reset been executed. The VF device can handle the reset request individually in it's reset work handler. This change updated gpu recover sequence to skip reset other device in the same hive for SRIOV VF. Signed-off-by:
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Aurabindo Pillai authored
[Why] Allow for disabling non transparent mode of LTTPR for running tests. [How] Add a feature flag and set them during init sequence. The flags are already being used in DC. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
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Tao Zhou authored
The RAS poison mode is enabled by default on the platform. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Fangzhi Zuo authored
It is to force SST sequence on MST capable receivers. v2: squash in compilation fix when CONFIG_DRM_AMD_DC_DCN is not set Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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- 07 Dec, 2021 20 commits
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Claudio Suarez authored
Once EDID is parsed, the monitor HDMI support information is available through drm_display_info.is_hdmi. The amdgpu driver still calls drm_detect_hdmi_monitor() to retrieve the same information, which is less efficient. Change to drm_display_info.is_hdmi This is a TODO task in Documentation/gpu/todo.rst Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Claudio Suarez <cssk@net-c.es> Signed-off-by:
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Claudio Suarez authored
Use drm_edid_get_monitor_name() instead of duplicating the code that parses the EDID in dm_helpers_parse_edid_caps() Reviewed-by:
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Claudio Suarez authored
drm_display_info is updated by drm_get_edid() or drm_connector_update_edid_property(). In the amdgpu driver it is almost always updated when the edid is read in amdgpu_connector_get_edid(), but not always. Change amdgpu_connector_get_edid() and amdgpu_connector_free_edid() to keep drm_display_info updated. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] During dcn31_stream_encoder_create, if PHYC/D get remapped to F/G on B0 then we'll index 5 or 6 into a array of length 5 - leading to an access violation on some configs during device creation. [How] Software won't be touching PHYF/PHYG directly, so just extend the array to cover all possible engine IDs. Even if it does by try to access one of these registers by accident the offset will be 0 and we'll get a warning during the access. Fixes: 2fe9a0e1 ("drm/amd/display: Fix DCN3 B0 DP Alt Mapping") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Stanley.Yang authored
remove in recovery stat check, skip umc ras err cnt harvest in amdgpu_ras_log_on_err_counter Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Flora Cui authored
Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Leslie Shi <Yuliang.Shi@amd.com> Reviewed-by:
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Flora Cui authored
Signed-off-by:
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Aric Cyr authored
Reduce stack usage by moving an unnecessary structure copy to a pointer. Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] To avoid hanging RDPCSPIPE when INTERCEPTB isn't set. DMCUB owns control of that bit so DMCUB should manage returning the information driver needs for link encoder control. [How] Add a new DMCUB command to return dp alt disable and dp4 information. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] A debug option is needed to temporarily force dp2 new link training fallback method for debugging purpose. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Oliver Logush authored
[why] Need to fix the code so it does not use reserved keywords [how] Change the total_length member of the cea struct Reviewed-by:
Oliver Logush <oliver.logush@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] Need to have dpia debug bits for configuring hpd delay. [How] Added hpd_delay_in_ms variable in dpia_debug_options. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Jude Shih authored
[Why] We shouldn't be accessing res_pool funcs from DM level, therefore, we should create API and let the flow be done in DC level. [How] We create new interface dp_get_link_enc to access and get the correct link_enc Reviewed-by:
Jude Shih <shenshih@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] crc_rd_wrk shouldn't be null in crc_win_update_set(). Current programming logic is inconsistent in crc_win_update_set(). [How] Initially, return if crc_rd_wrk is NULL. Later on, we can use member of crc_rd_wrk safely. Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Fixes: 9a65df19 ("drm/amd/display: Use PSP TA to read out crc") Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
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Mikita Lipski authored
[why/how] The function can be called on boot or after suspend when links are not initialized, to prevent it guard it with NULL pointer check Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
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Jarif Aftab authored
[WHY] -To ensure dc->res_pool has been initialized [HOW] -Check if dc->res_pool is true in the if statement Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Jarif Aftab <jaraftab@amd.com> Signed-off-by:
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Wyatt Wood authored
[Why] When HPD IRQ occurs, it triggers a PSR disable and reenable directly through dc layer. Since it does not pass through the power layer, the layer that tracks whether PSR is enabled or disabled and which masks are set, this layer is now out of sync with the real PSR state in FW. Theoretically PSR can be enabled during hw programming sequences or any other situation where we must disable PSR. [How] Check if PSR is enabled before doing PSR disable/reenable. Reviewed-by:
Wyatt Wood <wyatt.wood@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The HW interrupt gets disabled after S3/S4/reset so we don't receive notifications for HPD or AUX from DMUB - leading to timeout and black screen with (or without) DPIA links connected. [How] Re-enable the interrupt after S3/S4/reset like we do for the other DC interrupts. Guard both instances of the outbox interrupt enable or we'll hang during restore on ASIC that don't support it. Fixes: 524a0ba6 ("drm/amd/display: Fix DPIA outbox timeout after GPU reset") Reviewed-by:
Jude Shih <Jude.Shih@amd.com> Acked-by:
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George Shen authored
[Why] Certain LTTPR require output VS/PE to be explicitly set during PHY test automation. [How] Add vendor-specific sequence to set LTTPR output VS/PE. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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