- 17 Mar, 2011 22 commits
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Borislav Petkov authored
Replace per-DCT macros with smarter ones, drop hack and look for the spare rank on all chip selects on a channel. Signed-off-by:Borislav Petkov <borislav.petkov@amd.com>
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Borislav Petkov authored
Remove the channel interleave select bit properly. See F2x110[DctSelIntLvAddr] for details. Signed-off-by: -
Borislav Petkov authored
When node interleaving is enabled, a subset of the addr[14:12] bits has to be removed in order to get the normalized DCT address of the DRAM channel. The actual number of bits to remove is determined by F1x[1, 0][7C:40][IntlvEn]. Do this correctly. Signed-off-by: -
Borislav Petkov authored
On revC3 and revE Fam10h machines and later, non-interleaved graphics framebuffer memory under the 16G mark can be swapped with a region located at the bottom of memory so that the GPU can use the interleaved region and thus two channels. Add support for that. Signed-off-by: -
Borislav Petkov authored
The address bits from MC4_STATUS differ only between K8 and the rest so no need for a per-family method. No functional change. Signed-off-by: -
Borislav Petkov authored
Use the struct mce directly instead of copying from it into a custom struct err_regs. No functionality change. Signed-off-by: -
Borislav Petkov authored
The only difference is that F10h used to sport ganged DCTs and F15h doesn't so adjust the F10h routine and reuse it. Signed-off-by: -
Borislav Petkov authored
Remove unused defines, drop family names from define names. Signed-off-by: -
Borislav Petkov authored
Remove reporting of errors with UC bit set - this is done by the MCE decoding code anyway and this driver deals with DRAM ECC errors only. UC (NB uncorrectable error) doesn't necessarily mean it is a DRAM error. Remove unused macros while at it. Signed-off-by: -
Borislav Petkov authored
The fact whether we are chipkill capable or not does not have any bearing when computing the channel index on a ganged DCT configuration so remove that. Also, simplify debug statements. Finally, remove old error injection leftovers, while at it. Signed-off-by: -
Borislav Petkov authored
Remove family names from macro names, drop single bit defines and comment their meaning instead. No functional change. Signed-off-by: -
Borislav Petkov authored
Shorten macro names, remove family name from macros, fix macro arguments, shorten debug strings. No functionality change. Signed-off-by: -
Borislav Petkov authored
* Restrict DCT ganged mode check since only Fam10h supports it * Adjust DRAM type detection for BD since it only supports DDR3 * Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do that in read_mc_regs() * Cleanup comments and remove family names from register macros * Remove unused defines There should be no functional change resulting from this patch. Signed-off-by: -
Borislav Petkov authored
Do not read DBAM regs twice and simplify code around them. There should be no functional change resulting from this patch. Signed-off-by: -
Borislav Petkov authored
Replace hard to read hex constants with a continuous masks macro. Signed-off-by: -
Borislav Petkov authored
This function maps the system address to the normalized DCT address. Document what the code does for more clarity and wrap insane bitmasks in a more understandable macro which generates them. Also, reduce number of arguments passed to the function. Finally, rename this function to what it actually does. No functional change. Signed-off-by: -
Borislav Petkov authored
Cleanup and simplify f10_determine_channel(); make it more readable. Also drop f10_map_intlv_en_to_shift() in favor of simply counting the bits in F1x124[DramIntlvEn] which is equivalent. There should be no functionality change resulting from this patch. Signed-off-by: -
Borislav Petkov authored
Add a struct representing the DRAM chip select base/limit register pairs. Concentrate all CS handling in a single function. Also, add CS looping macros for cleaner, more readable code. While at it, adjust code to F15h. Finally, do smaller macro names cleanups (remove family names from register macros) and debug messages clarification. No functional change. Signed-off-by: -
Borislav Petkov authored
Adjust to F15h, simplify code, fixup macros. Signed-off-by: -
Borislav Petkov authored
Add a struct representing the DRAM base/limit range pairs and remove all cached subfields. Replace them with accessor functions, which actually saves us some space: text data bss dec hex filename 14712 1577 336 16625 40f1 drivers/edac/amd64_edac_mod.o.after 14831 1609 336 16776 4188 drivers/edac/amd64_edac_mod.o.before Also, it simplifies the code a lot allowing to merge the K8 and F10h routines. No functional change. Signed-off-by: -
Borislav Petkov authored
F15h "multiplexes" between the configuration space of the two DRAM controllers by toggling D18F1x10C[DctCfgSel] while F10h has a different set of registers for DCT0, and DCT1 in extended PCI config space. Add DCT configuration space accessors per family thus wrapping all the different access prerequisites. Clean up code while at it, shorten names. Signed-off-by: -
Borislav Petkov authored
Raise the debug level of these routines so that their output get issued out only when the highest debug level is selected. Otherwise, don't pollute driver debug output. Signed-off-by:
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- 15 Mar, 2011 1 commit
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Linus Torvalds authored
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- 14 Mar, 2011 17 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300Linus Torvalds authored
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: MN10300: atomic_read() should ensure it emits a load MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not exist MN10300: Proper use of macros get_user() in the case of incremented pointers
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git://git.linux-mips.org/pub/scm/upstream-linusLinus Torvalds authored
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (26 commits) MIPS: Alchemy: Fix reset for MTX-1 and XXS1500 MIPS: MTX-1: Make au1000_eth probe all PHY addresses MIPS: Jz4740: Add HAVE_CLK MIPS: Move idle task creation to work queue MIPS, Perf-events: Use unsigned delta for right shift in event update MIPS, Perf-events: Work with the new callchain interface MIPS, Perf-events: Fix event check in validate_event() MIPS, Perf-events: Work with the new PMU interface MIPS, Perf-events: Work with irq_work MIPS: Fix always CONFIG_LOONGSON_UART_BASE=y MIPS: Loongson: Fix potentially wrong string handling MIPS: Fix GCC-4.6 'set but not used' warning in arch/mips/mm/init.c MIPS: Fix GCC-4.6 'set but not used' warning in ieee754int.h MIPS: Remove unused code from arch/mips/kernel/syscall.c MIPS: Fix GCC-4.6 'set but not used' warning in signal*.c MIPS: MSP: Fix MSP71xx bpci interrupt handler return value MIPS: Select R4K timer lib for all MSP platforms MIPS: Loongson: Remove ad-hoc cmdline default MIPS: Clear the correct flag in sysmips(MIPS_FIXADE, ...). MIPS: Add an unreachable return statement to satisfy buggy GCCs. ...
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Linus Torvalds authored
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: ce4100: Set pci ops via callback instead of module init x86/mm: Fix pgd_lock deadlock x86/mm: Handle mm_fault_error() in kernel space x86: Don't check for BIOS corruption in first 64K when there's no need to
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Linus Torvalds authored
This reverts the parent commit. I hate doing that, but it's generating some discussion ("half of it is right"), and since I am planning on doing the 2.6.38 release later today we can punt it to stable if required. Let's not rock the boat right now. Signed-off-by:Linus Torvalds <torvalds@linux-foundation.org>
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Oleg Nesterov authored
oom_kill_process() starts with victim_points == 0. This means that (most likely) any child has more points and can be killed erroneously. Also, "children has a different mm" doesn't match the reality, we should check child->mm != t->mm. This check is not exactly correct if t->mm == NULL but this doesn't really matter, oom_kill_task() will kill them anyway. Note: "Kill all processes sharing p->mm" in oom_kill_task() is wrong too. Signed-off-by:
Oleg Nesterov <oleg@redhat.com> Signed-off-by:
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Florian Fainelli authored
Since commit 32fd6901 (MIPS: Alchemy: get rid of common/reset.c) Alchemy-based boards use their own reset function. For MTX-1 and XXS1500, the reset function pokes at the BCSR.SYSTEM_RESET register, but this does not work. According to Bruno Randolf, this was not tested when written. Previously, the generic au1000_restart() routine called the board specific reset function, which for MTX-1 and XXS1500 did not work, but finally made a jump to the reset vector, which really triggers a system restart. Fix reboot for both targets by jumping to the reset vector. Signed-off-by:
Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2093/Acked-by:
Bruno Randolf <br1@einfach.org> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Florian Fainelli authored
When au1000_eth probes the MII bus for PHY address, if we do not set au1000_eth platform data's phy_search_highest_address, the MII probing logic will exit early and will assume a valid PHY is found at address 0. For MTX-1, the PHY is at address 31, and without this patch, the link detection/speed/duplex would not work correctly. CC: stable@kernel.org Signed-off-by:
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Maurus Cuelenaere authored
Jz4740 supports the clock framework but doesn't have HAVE_CLK defined, so define it! Signed-off-by:
Maurus Cuelenaere <mcuelenaere@gmail.com> To: linux-mips@linux-mips.org To: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2112/Acked-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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Maksim Rayskiy authored
To avoid forking usermode thread when creating an idle task, move fork_idle to a work queue. If kernel starts with maxcpus= option which does not bring all available cpus online at boot time, idle tasks for offline cpus are not created. If later offline cpus are hotplugged through sysfs, __cpu_up is called in the context of the user task, and fork_idle copies its non-zero mm pointer. This causes BUG() in per_cpu_trap_init. This also avoids issues with resource limits of the CPU writing to sysfs, containers, maybe others. Signed-off-by:
Maksim Rayskiy <mrayskiy@broadcom.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2070/Signed-off-by:
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Deng-Cheng Zhu authored
Leverage the commit for ARM by Will Deacon: - 446a5a8b ARM: 6205/1: perf: ensure counter delta is treated as unsigned Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Acked-by:
Will Deacon <will.deacon@arm.com> Acked-by:
David Daney <ddaney@caviumnetworks.com> Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: a.p.zijlstra@chello.nl To: fweisbec@gmail.com To: will.deacon@arm.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: matt@console-pimps.org Cc: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/2015/Signed-off-by:
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Deng-Cheng Zhu authored
This is the MIPS part of the following commits by Frederic Weisbecker: - f72c1a93 perf: Factorize callchain context handling Store the kernel and user contexts from the generic layer instead of archs, this gathers some repetitive code. - 56962b44 perf: Generalize some arch callchain code - Most archs use one callchain buffer per cpu, except x86 that needs to deal with NMIs. Provide a default perf_callchain_buffer() implementation that x86 overrides. - Centralize all the kernel/user regs handling and invoke new arch handlers from there: perf_callchain_user() / perf_callchain_kernel() That avoid all the user_mode(), current->mm checks and so... - Invert some parameters in perf_callchain_*() helpers: entry to the left, regs to the right, following the traditional (dst, src). - 70791ce9 perf: Generalize callchain_store() callchain_store() is the same on every archs, inline it in perf_event.h and rename it to perf_callchain_store() to avoid any collision. This removes repetitive code. - c1a65932 perf: Drop unappropriate tests on arch callchains Drop the TASK_RUNNING test on user tasks for callchains as this check doesn't seem to make any sense. Also remove the tests for !current that is not supposed to happen and current->pid as this should be handled at the generic level, with exclude_idle attribute. Reported-by:
Wu Zhangjin <wuzhangjin@gmail.com> Acked-by:
Frederic Weisbecker <fweisbec@gmail.com> Acked-by:
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Deng-Cheng Zhu authored
Ignore events that are in off/error state or belong to a different PMU. This patch originates from the following commit for ARM by Will Deacon: - 65b4711f ARM: 6352/1: perf: fix event validation The validate_event function in the ARM perf events backend has the following problems: 1.) Events that are disabled count towards the cost. 2.) Events associated with other PMUs [for example, software events or breakpoints] do not count towards the cost, but do fail validation, causing the group to fail. This patch changes validate_event so that it ignores events in the PERF_EVENT_STATE_OFF state or that are scheduled for other PMUs. Acked-by:
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Deng-Cheng Zhu authored
This is the MIPS part of the following commits by Peter Zijlstra: - a4eaf7f1 perf: Rework the PMU methods Replace pmu::{enable,disable,start,stop,unthrottle} with pmu::{add,del,start,stop}, all of which take a flags argument. The new interface extends the capability to stop a counter while keeping it scheduled on the PMU. We replace the throttled state with the generic stopped state. This also allows us to efficiently stop/start counters over certain code paths (like IRQ handlers). It also allows scheduling a counter without it starting, allowing for a generic frozen state (useful for rotating stopped counters). The stopped state is implemented in two different ways, depending on how the architecture implemented the throttled state: 1) We disable the counter: a) the pmu has per-counter enable bits, we flip that b) we program a NOP event, preserving the counter state 2) We store the counter state and ignore all read/overflow events For MIPSXX, the stopped state is implemented in the way of 1.b as above. - 33696fc0 perf: Per PMU disable Changes perf_disable() into perf_pmu_disable(). - 24cd7f54 perf: Reduce perf_disable() usage Since the current perf_disable() usage is only an optimization, remove it for now. This eases the removal of the __weak hw_perf_enable() interface. - b0a873eb perf: Register PMU implementations Simple registration interface for struct pmu, this provides the infrastructure for removing all the weak functions. - 51b0fe39 perf: Deconstify struct pmu sed -ie 's/const struct pmu\>/struct pmu/g' `git grep -l "const struct pmu\>"` Reported-by:
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Deng-Cheng Zhu authored
This is the MIPS part of the following commit by Peter Zijlstra: - e360adbe irq_work: Add generic hardirq context callbacks Provide a mechanism that allows running code in IRQ context. It is most useful for NMI code that needs to interact with the rest of the system -- like wakeup a task to drain buffers. Perf currently has such a mechanism, so extract that and provide it as a generic feature, independent of perf so that others may also benefit. The IRQ context callback is generated through self-IPIs where possible, or on architectures like powerpc the decrementer (the built-in timer facility) is set to generate an interrupt immediately. Architectures that don't have anything like this get to do with a callback from the timer tick. These architectures can call irq_work_run() at the tail of any IRQ handlers that might enqueue such work (like the perf IRQ handler) to avoid undue latencies in processing the work. For MIPSXX, we need to call irq_work_run() at the tail of the perf IRQ handler as described above. Reported-by:
Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by:
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Yoichi Yuasa authored
Signed-off-by:
Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2055/Signed-off-by:
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Stefan Weil authored
This error was reported by cppcheck: arch/mips/loongson/common/machtype.c:56: error: Dangerous usage of 'str' (strncpy doesn't always 0-terminate it) If strncpy copied MACHTYPE_LEN bytes, the destination string str was not terminated. The patch adds one more byte to str and makes sure that this byte is always 0. Signed-off-by:
Stefan Weil <weil@mail.berlios.de> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Arnaud Patard <apatard@mandriva.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2053/Signed-off-by:
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David Daney authored
Under some combinations of CONFIG_*, lastpfn in page_is_ram is 'set but not used'. Mark it as __maybe_unused to quiet the warning/error. Signed-off-by:
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