- 15 May, 2018 40 commits
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Rex Zhu authored
It is caused by 'commit d6c9a7dc86cd ("drm/amd/pp: Move common code to smu_helper.c")' Reviewed-by:Evan Quan <evan.quan@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Chunming Zhou authored
Otherwise, cpu stuck for 22s with kernel panic. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Marek Olšák authored
There is a new IB flag that enables this new behavior. Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense when draw calls from two adjacent gfx IBs run in parallel. This will be the new default for Mesa. v2: bump the version Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Chunming Zhou authored
if domain is illegal, we should return error. v2: remove duplicated domain checking. Signed-off-by:
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Chunming Zhou authored
When GEM needs to fallback to GTT for VRAM BOs we still want the preferred domain to be untouched so that the BO has a cance to move back to VRAM in the future. Signed-off-by:
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Christian König authored
Turned out that this locks up some bare metal Vega10. v2: fix stupid typo Signed-off-by:
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Pixel Ding authored
Make sure main thread won't update last_sched fence when entity is cleanup. Fix a racing issue which is caused by putting last_sched fence twice. Running vulkaninfo in tight loop can produce this issue as seeing wild fence pointer. v2: squash in build fix (Christian) Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Pixel Ding authored
Fix the potential memleak since scheduler main thread always hold one last_sched fence. Signed-off-by:
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Alex Deucher authored
Useful for info gathering about what firmwares are in use in the driver. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Rex Zhu authored
Make sure to update the MCLK and SCLK flags when setting the VDDC flags due to dependencies. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
v2: check reserved vram size before allocate. Reviewed-by:
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Chunming Zhou authored
After that, we can easily add new parameter when need. v2: a) rebase. b) Initialize struct amdgpu_bo_param, future new member could only be used in some one case, but all member should have its own initial value. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Cc: christian.koenig@amd.com Cc: Felix.Kuehling@amd.com Signed-off-by:
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Chunming Zhou authored
amdgpu_bo_create has too many parameters, and used in too many places. Collect them to one structure. Signed-off-by:
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Yongqiang Sun authored
Linux doesn't know lid state, better to check dig enable value from register. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Yongqiang Sun authored
Use lid state only to determine fast boot optimization is not enough. For S3/Resume, due to bios isn't involved in boot, eDP wasn't light up, while lid state is open, if do fast boot optimization, eDP panel will skip enable link and result in black screen after boot. And becasue of bios isn't involved, no matter UEFI or Legacy boot, BIOS_SCRATCH_3 value should be 0, use this to determine the case. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Eric Bernstein authored
Added dchububu.h header file for common enum/struct definitions. Added new interface functions get_dcc_compression_cap, dcc_support_swizzle, dcc_support_pixel_format. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Yongqiang Sun authored
For legacy enable boot up with lid closed, eDP information couldn't be read correctly via SBIOS_SCRATCH_3 results in eDP cannot be light up properly when open lid. Check lid state instead can resolve the issue. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Leo (Sunpeng) Li authored
Hardware understands the regamma LUT as a piecewise linear function, with points spaced exponentially along the range. We previously programmed the LUT for range [2^-10, 2^0). This causes (normalized) color values of 1 (=2^0) to miss the programmed LUT, and fall onto the end region. For DCE, the end region is extrapolated using a single (base, slope) pair, using the max y-value from the last point in the curve as base. This presents a problem, since this value affects all three color channels. Scaling down the intensity of say - the blue regamma curve - will not affect it's end region. This is especially noticiable when using RedShift. It scales down the blue and green channels, but leaves full-intensity colors unshifted. Therefore, extend the range to cover [2^-10, 2^1) by programming another hardware segment, containing only one point. That way, we won't be hitting the end region. Note that things are a bit different for DCN, since the end region can be set per-channel. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Roman Li authored
Adding missing call to cache current backlight values. Otherwise the brightness resets to default value on resume. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Eric Yang authored
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Harry Wentland authored
Even though this is required for degamma since DCE HW only supports a couple predefined LUTs we can just program the LUT directly for regamma. This fixes dark screens which occurs when we program regamma to bypass while degamma is using srgb LUT. Signed-off-by:
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Shirish S authored
amdgpu_ib_ring_tests() runs test IB's on rings at boot contributes to ~500 ms of amdgpu driver's boot time. This patch defers it and ensures that its executed in amdgpu_info_ioctl() if it wasn't scheduled. V2: Use queue_delayed_work() & flush_delayed_work(). V3: removed usage of separate wq, ensure ib tests is run before enabling clockgating. Signed-off-by:Shirish S <shirish.s@amd.com> Reviewed-by:
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Mikita Lipski authored
Filling the smu10_store_cc6_data based on the implementation of Windows Powerplay. There is an uncertainty with one of the parameters passed to the function pstate_switch_disable - is not a part of smu10 private data structure. So in the function its just ignored. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Mikita Lipski authored
The function is never implemented for raven on linux. It follows similair implementation as on windows. SMU still needs to notify SMC and copy WM table, which is added here. But on other Asics such as Vega this step is not implemented. Signed-off-by:
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Christian König authored
If a per VM BO ends up in a allowed domain it never moves back into the prefered domain. v2: move the extra handling into amdgpu_vm_bo_update when we exit the state machine. Make memory type handling generic. Signed-off-by: -
Christian König authored
This reverts commit 7d1ca1325260a9e9329b10a21e3692e6f188936f. Makes fallback handling to complicated. This is just a feature for the GEM interface and shouldn't leak into the core BO create function. The intended change to preserve the preferred domains is implemented in a follow up patch. Signed-off-by:
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Christian König authored
This reverts commit 6f51d28bfe8e1a676de5cd877639245bed3cc818. Makes fallback handling to complicated. This is just a feature for the GEM interface and shouldn't leak into the core BO create function. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
smu firmware do not update response register immediately under some delay tasks, we may read out the original value. so need to clear the register before send smu message. Acked-by:
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Rex Zhu authored
Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, User need to set start time and end time, firmware can calculate the average vddc/vddci/max power. but the type of return values is not unified. For Vi, return type is uint. For vega, return type is float. so this struct can't be suitable for all asics. Acked-by:
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Rex Zhu authored
pkgpwr is the average gpu power of 100ms. it is calculated by firmware in real time. 1. we can send smu message PPSMC_MSG_GetCurrPkgPwr to read currentpkgpwr directly. 2. On Fiji/tonga/bonaire/hawwii, without PPSMC_MSG_GetCurrPkgPwr support. Send PPSMC_MSG_PmStatusLogStart/Sample to let smu write currentpkgpwr to ixSMU_PM_STATUS_94. driver can read pkgpwr from ixSMU_PM_STATUS_94. Acked-by:
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