- 30 Aug, 2013 40 commits
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Alex Deucher authored
convert from number of lanes to register setting. Signed-off-by:Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Used for vce power management. Signed-off-by: -
Alex Deucher authored
Required for dpm on CI. Signed-off-by: -
Alex Deucher authored
Needed for DPM on CI. Signed-off-by: -
Alex Deucher authored
Uses a different table format if the board supports EVV. Signed-off-by: -
Alex Deucher authored
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Alex Deucher authored
This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: -
Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
No support for reading temperature back yet. Signed-off-by: -
Alex Deucher authored
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Alex Deucher authored
Used for uvd power management. Signed-off-by: -
Alex Deucher authored
Internally we switched to using a separate header for atombios pplib definitions. Switch over the open source driver. Signed-off-by: -
Alex Deucher authored
Needed for DPM on KB/KV. Signed-off-by: -
Alex Deucher authored
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Alex Deucher authored
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: -
Alex Deucher authored
and remove duplicate si_rlc functions. Signed-off-by: -
Alex Deucher authored
This will eventually be shared with newer asics to reduce code duplication. Signed-off-by: -
Alex Deucher authored
Restructure rlc setup to handle clock and power gating. Signed-off-by: -
Alex Deucher authored
Enables PCIE ASPM (Active State Power Management) on CIK asics. Signed-off-by: -
Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Required for DPM on CIK. Signed-off-by: -
Alex Deucher authored
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: -
Alex Deucher authored
Newer asics don't have specific UVD states. Signed-off-by: -
Alex Deucher authored
Newer asics have a lot of vram so it's less of an issue to waste a little more space for the gart page table. This gives us some additional gart space before having to migrate to non-gart system ram for games, etc. where we use up most of vram. Signed-off-by: -
Alex Deucher authored
1. Handle the the thermal state directly in the work handler. Remove the state selection function since nothing else uses it now. 2. On some asics there is no thermal state, so we just use a regular state and force the low performance state. Signed-off-by: -
Alex Deucher authored
Use the UVD handle information to determine which which power states to select when using UVD. For example, decoding a single SD stream requires much lower clocks than multiple HD streams. v2: switch to a cleaner dpm/uvd interface v3: change the uvd power state while streams are active if need be Signed-off-by: -
Alex Deucher authored
Add a helper function for counting the number of open stream handles. v2: fix copy-pasta in comments and whitespace error v3: make function static since it's only used in radeon_uvd.c at the moment v4: make non-static again for future changes v5: make static again for new rework of dpm uvd changes Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
No longer used now that we use the async dma engines or CP DMA for bo copies. Signed-off-by: -
Alex Deucher authored
CP DMA is lighter weight than using the 3D engine. Signed-off-by: -
Alex Deucher authored
This LCD monitor (1280x1024 native) has a completely bogus detailed timing (640x350@70hz). User reports that 1280x1024@60 has waves so prefer 1280x1024@75. Manufacturer: MED Model: 7b8 Serial#: 99188 Year: 2005 Week: 5 EDID Version: 1.3 Analog Display Input, Input Voltage Level: 0.700/0.700 V Sync: Separate Max Image Size [cm]: horiz.: 34 vert.: 27 Gamma: 2.50 DPMS capabilities: Off; RGB/Color Display First detailed timing is preferred mode redX: 0.645 redY: 0.348 greenX: 0.280 greenY: 0.605 blueX: 0.142 blueY: 0.071 whiteX: 0.313 whiteY: 0.329 Supported established timings: 720x400@70Hz 640x480@60Hz 640x480@72Hz 640x480@75Hz 800x600@56Hz 800x600@60Hz 800x600@72Hz 800x600@75Hz 1024x768@60Hz 1024x768@70Hz 1024x768@75Hz 1280x1024@75Hz Manufacturer's mask: 0 Supported standard timings: Supported detailed timing: clock: 25.2 MHz Image Size: 337 x 270 mm h_active: 640 h_sync: 688 h_sync_end 784 h_blank_end 800 h_border: 0 v_active: 350 v_sync: 350 v_sync_end 352 v_blanking: 449 v_border: 0 Monitor name: MD30217PG Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz Serial No: 501099188 EDID (in hex): 00ffffffffffff0034a4b80774830100 050f010368221b962a0c55a559479b24 125054afcf00310a0101010101018180 000000000000d60980a0205e63103060 0200510e1100001e000000fc004d4433 3032313750470a202020000000fd0038 4c1e530e000a202020202020000000ff 003530313039393138380a2020200078 Signed-off-by:
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