- 07 Aug, 2023 3 commits
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Rob Clark authored
Even in the ocmem case, the allocated ocmem buffer size should match the requested size. v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition. Signed-off-by:Rob Clark <robdclark@chromium.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549759/
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Rob Clark authored
No real need to have marketing names in the kernel. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
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Rob Clark authored
Back-merge msm-fixes to resolve conflicts. Signed-off-by:
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- 04 Aug, 2023 5 commits
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Dmitry Baryshkov authored
Since commit 1e7ac595 ("drm/msm/dpu: pass irq to dpu_encoder_helper_wait_for_irq()") the dpu_encoder_phys_wb_wait_for_commit_done expects the IRQ index rather than the IRQ index in phys_enc->intr table, however writeback got the older invocation in place. This was unnoticed for several releases, but now it's time to fix it. Fixes: d7d0e73f ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by:
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Dmitry Baryshkov authored
When removing the core perf tune overrides, I also occasionaly removed the initialisation of the clk_rate variable. Initialise it to 0 to let max() correctly calculate the maximum of requested clock rates. Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Fixes: 6a4bc739 ("drm/msm/dpu: drop separate dpu_core_perf_tune overrides") Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/551321/ Link: https://lore.kernel.org/r/20230804094804.36053-1-dmitry.baryshkov@linaro.org
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Jiapeng Chong authored
No functional modification involved. drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:183 dpu_core_perf_crtc_check() warn: inconsistent indenting. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6096Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reviewed-by:
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Daniel Vetter authored
Apparently no one noticed that mdp5 plane states leak like a sieve ever since we introduced plane_state->commit refcount a few years ago in 21a01abb ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Fix it by using the right helpers. Fixes: 21a01abb ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Rob Clark <robdclark@gmail.com> Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Reported-and-tested-by: dorum@noisolation.com Cc: dorum@noisolation.com Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Reviewed-by:
Rob Clark <robdclark@gmail.com> Reviewed-by:
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Jessica Zhang authored
Drop vsync_event and vsync_event_work handlers as they are unnecessary. In addition drop the dpu_enc_ktime_template event class as it will be unused after the vsync_event handlers are dropped. Signed-off-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by:
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- 03 Aug, 2023 3 commits
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Dmitry Baryshkov authored
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be 0x100, while the actual length is 0x9c (last register having offset 0x98). Reduce subblock length to remove the empty register space from being dumped. Fixes: 0d1b10c6 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length. This includes the common block itself, enc subblocks and some empty space around. Change that to pass 0x4 instead, the length of common register block itself. Fixes: 0d1b10c6 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reported-by:
Ryan McCann <quic_rmccann@quicinc.com> Reviewed-by:
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Jonathan Marek authored
sm8550 has 16 vbif clients. This fixes the extra 2 clients (DMA4/DMA5) not having their memtype initialized. This fixes DMA4/DMA5 planes not displaying correctly. Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550") Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Reviewed-by:
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- 02 Aug, 2023 24 commits
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Dmitry Baryshkov authored
This function does nothing, just clears one struct field. Drop it now. Acked-by:
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Dmitry Baryshkov authored
dpu_core_perf should not make decisions on the maximum possible core clock rate. Pass the value from dpu_kms_hw_init() and drop handling of core_clk from dpu_core_perf.c Reviewed-by:
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Dmitry Baryshkov authored
The dev_pm_opp_set_rate() already contains a call for clk_round_rate for the passed value. Stop calling it manually from _dpu_core_perf_get_core_clk_rate(). It is slightly incorrect to call it this way, as we should round the final calculated clock rate rather than rounding all the intermediate values. Reviewed-by:
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Dmitry Baryshkov authored
Remove dpu_core_perf::dev and dpu_core_perf::debugfs_root fields, they are not used by the code. Reviewed-by:
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Dmitry Baryshkov authored
Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using full-featured catalog data. Acked-by:
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Dmitry Baryshkov authored
The stop_req is true only in the dpu_crtc_disable() case, when crtc->enable has already been set to false. This renders the stop_req argument useless. Remove it completely. Reviewed-by:
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Dmitry Baryshkov authored
dpu_core_perf.c contains several multi-line conditions which are hard to comprehent because of the indentation. Rework the identation of these conditions to make it easier to understand them. Reviewed-by:
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Dmitry Baryshkov authored
The values in struct dpu_core_perf_tune are fixed per the core perf mode. Drop the 'tune' values and substitute them with known values when performing perf management. Note: min_bus_vote was not used at all, so it is just silently dropped. Reviewed-by:
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Dmitry Baryshkov authored
Skip bandwidth aggregation and return early if there are no interconnect paths defined for the DPU device. Signed-off-by:
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Dmitry Baryshkov authored
Drop the leftover of bus-client -> interconnect conversion, the enum dpu_core_perf_data_bus_id. Fixes: cb88482e ("drm/msm/dpu: clean up references of DPU custom bus scaling") Reviewed-by:
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Dmitry Baryshkov authored
The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are not used by the driver, drop them completely. Signed-off-by:
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Dmitry Baryshkov authored
As the DPU driver has switched to fetching data from MDSS driver, we can now drop the UBWC and highest_bank_bit parts of the DPU hw catalog. Reviewed-by:
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Dmitry Baryshkov authored
Switch to using data from MDSS driver to program the SSPP fetch and UBWC configuration. As a side-effect, this also swithes the DPU driver from DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects the hardware register values. Signed-off-by:
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Dmitry Baryshkov authored
As we are going to use MDSS data for DPU programming, populate missing MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS programming, so skip them. Signed-off-by:
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Dmitry Baryshkov authored
DPU programming requires knowledge of some of UBWC parameters. This results in duplication of UBWC data between MDSS and DPU drivers. Export the required data from MDSS driver. Reviewed-by:
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Dmitry Baryshkov authored
Rename the ubwc_version field to ubwc_enc_version, it denotes the version of the UBWC encoder, not the "UBWC version". Reviewed-by:
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Dmitry Baryshkov authored
The SM8550 platform employs newer UBWC decoder, which requires slightly different programming. Fixes: a2f33995 ("drm/msm: mdss: add support for SM8550") Signed-off-by:
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Dmitry Baryshkov authored
While reworking interrupts masks, it was easier to keep old MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time to drop them and use unified symbol names. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Dmitry Baryshkov authored
Now as the list of the interrupts is constructed from the catalog data, drop the mdss_irqs field from catalog. Reviewed-by:
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Dmitry Baryshkov authored
Declaring the mask of supported interrupts proved to be error-prone. It is very easy to add a bit with no corresponding backing block or to miss the INTF TE bit. Replace this with looping over the enabled INTF blocks to setup the irq mask. Reviewed-by:
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Dmitry Baryshkov authored
There is no point in having a single enum (and a single array) for both DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single enum and two IRQ address arrays. Reviewed-by:
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Dmitry Baryshkov authored
Inline __intr_offset(), there is no point in having a separate oneline function for setting base block address. Reviewed-by:
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Ruan Jinjie authored
There is no need to call the DRM_DEV_ERROR() function directly to print a custom message when handling an error from platform_get_irq() function as it is going to display an appropriate error message in case of a failure. Signed-off-by:
Ruan Jinjie <ruanjinjie@huawei.com> Reviewed-by:
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Amit Pundir authored
Add and document the reserved memory region property in the mdss-common schema. For now (sdm845-db845c), it points to a framebuffer memory region reserved by the bootloader for splash screen. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Amit Pundir <amit.pundir@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549376/ Link: https://lore.kernel.org/r/20230726132719.2117369-1-amit.pundir@linaro.orgSigned-off-by:
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- 27 Jul, 2023 5 commits
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Marijn Suijten authored
SM6125 features only a single PHY (despite a secondary PHY PLL source being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream sources for this "trinket" SoC do not define the typical "vcca" regulator to be available nor used. This, including the register offset is identical to QCM2290, whose config struct can trivially be reused. Reviewed-by:
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Marijn Suijten authored
Document availability of the 14nm DSI PHY on SM6125. Note that this compatible uses the SoC-suffix variant, intead of postfixing an arbitrary number without the sm/sdm portion. The PHY is not powered by a vcca regulator like on most SoCs, but by the MX power domain that is provided via the power-domains property and a single corresponding required-opps. Acked-by:
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Marijn Suijten authored
SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder. Reviewed-by:
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Marijn Suijten authored
Add definitions for the display hardware used on the Qualcomm SM6125 platform. Reviewed-by:
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Marijn Suijten authored
Document the SM6125 MDSS. Reviewed-by:
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