- 04 Dec, 2014 1 commit
-
-
Tomeu Vizoso authored
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
- 03 Dec, 2014 4 commits
-
-
Tomeu Vizoso authored
Instead of struct clk, as this should be only used by providers. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
Tomeu Vizoso authored
As it's only used internally, in drivers/clk/clk.c. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
Tomeu Vizoso authored
As __clk_release could call kfree on clk and then we wouldn't have a safe way of getting the module that owns the clock. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Fixes: fcb0ee6a ("clk: Implement clk_unregister") Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
Tomeu Vizoso authored
Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
- 29 Nov, 2014 2 commits
-
-
Michael Turquette authored
Merge tag 'ib-mfd-regulator-clk-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into clk-next Immutable branch between MFD, Regulator and Clk, due for v3.19
-
Michael Turquette authored
Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next - clock phase setting capability for the rk3288 mmc clocks - pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers
-
- 27 Nov, 2014 3 commits
-
-
Alexandru M Stan authored
This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Alexandru M Stan <amstan@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
Alexandru M Stan authored
These clocks represent the physical clocks (including phases) and they will later be used for clock phase tuning. Suggested-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Alexandru M Stan <amstan@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
Sonny Rao authored
This exposes the clock that comes out of the i2s block which generally goes to the audio codec. Signed-off-by:
Sonny Rao <sonnyrao@chromium.org> [removed CLK_SET_RATE_PARENT from original patch] Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
- 26 Nov, 2014 3 commits
-
-
Jeff Chen authored
The DMC clocks need to be turned off at runtime. Use the newly assigned clock IDs to export them. Signed-off-by:
Jeff Chen <cym@rock-chips.com> [dianders: split into two patches; adjusted commit msg] Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
Jeff Chen authored
The DMC clocks need to be turned off at runtime, so we should have IDs so we can export them. Signed-off-by:
Jeff Chen <cym@rock-chips.com> [dianders: split into two patches; adjusted commit msg] Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
kbuild test robot authored
drivers/clk/clk-s2mps11.c:181:2-3: Unneeded semicolon Removes unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
- 25 Nov, 2014 10 commits
-
-
Chanwoo Choi authored
This patch adds the binding documentation for Samsung S2MPS13 PMIC which is similiar with existing S2MPS14 PMIC. S2MPS13 has the different number of regulators from S2MPS14 and RTC/Clock is the same with the S2MPS14. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Acked-by:
Sangbeom Kim <sbkim73@samsung.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
-
Chanwoo Choi authored
This patch adds the support for S2MPS13 PMIC clock which is same with existing S2MPS14 RTC IP. But, S2MPS13 uses all of clocks (32khz_{ap|bt|cp}). Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by:
Michael Turquette <mturquette@linaro.org> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
-
Chanwoo Choi authored
This patch adds S2MPS13 regulator device to existing S2MPS11 device driver. The S2MPS13 has just different number of regulators from S2MPS14. The S2MPS13 regulator device includes LDO[1-40] and BUCK[1-10]. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Acked-by:
Sangbeom Kim <sbkim73@samsung.com> Acked-by:
Mark Brown <broonie@kernel.org> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
-
Chanwoo Choi authored
This patch adds the support for Samsung S2MPS13 PMIC device to the sec-core MFD driver. The S2MPS13 is very similar with existing S2MPS14 and includes PMIC/ RTC/CLOCK devices. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Acked-by:
Sangbeom Kim <sbkim73@samsung.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
-
Heiko Stuebner authored
Add the new flag to gpll and cpll on rk3188 and similar and to gpll, cpll and npll on rk3288. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com> Tested-by:
Kever Yang <kever.yang@rock-chips.com>
-
Heiko Stuebner authored
In some cases firmware brings up plls with different parameters than the ones noted in the rate table for the specific frequency. These firmware-selected parameters are worse than the tested ones in the pll rate tables but cannot be changed by a simple clk_set_rate call when the rate stays the same. Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback that checks the runtime-parameters against the matching rate table entry and adjusts them to the table-ones if necessary. If no rate table is set or the current rate does not match any rate-table entry no changes are made. Being able to limit this adjustment to specific plls is necessary to not touch the ones supplying core components like the apll and dpll supplying the armcores and dram. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com> Tested-by:
Kever Yang <kever.yang@rock-chips.com>
-
Heiko Stuebner authored
In some cases we might need to access the data of the pll mux before the actual mux gets registered - like in the following patch adding an init-callback. Therefore populate pll_mux before registering the core pll-clock. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com> Tested-by:
Kever Yang <kever.yang@rock-chips.com>
-
Heiko Stuebner authored
This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com> Tested-by:
Kever Yang <kever.yang@rock-chips.com>
-
Michael Turquette authored
Merge tag 'sunxi-clocks-for-3.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner Clocks additions for 3.19 A few patches that should go through the clock tree, mostly fixes, cleanups, and new clocks additions to start to support the A80.
-
Michael Turquette authored
-
- 23 Nov, 2014 7 commits
-
-
Hans de Goede authored
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk has 2 bits selecting between 3 possible parents using values of 0, 1, 2, which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in its flag. However we do not support parent 1 (an external clock), so use a table to select parent 0 or 2, which are the 2 parents we support. Note this has not been causing any issues sofar, because we start with a parent setting of parent 0, and only ever re-parent to parent 2 (for which we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set we write a value of 2 for index 1. Tested on both a cubietruck (which uses rgmii mode) as well as a cs908 (an a31s board which uses mii mode). Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Chen-Yu Tsai authored
Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2. This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Chen-Yu Tsai authored
Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks. On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered. This patch adds an entry for the number of child clocks alongside the data structures for them. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Chen-Yu Tsai authored
This driver does not match the hardware, which is actually compatible to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop this driver. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Chen-Yu Tsai authored
The apb2 clocks are actually the same as apb1 clocks on the other sunxi platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk". Update the dtsi to use the new unified apb1 clk. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Emilio López authored
With the new factors infrastructure in place, we can unify apb1 and apb1_mux as a single clock now. Signed-off-by:
Emilio López <emilio@elopez.com.ar> [wens@csie.org: Change apb1 node label to "apb1"; reword commit title] Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Julien CHAUVEAU authored
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11). Signed-off-by:
Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
- 22 Nov, 2014 1 commit
-
-
Julien CHAUVEAU authored
In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13. This appears to be a copy-paste error because such a register does not exist. We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock is the same as the rk3066 spdif clock, so we move it to the common clock branches. Signed-off-by:
Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
- 20 Nov, 2014 1 commit
-
-
Bintian Wang authored
Use __initconst instead of __initdata for constant init data. Signed-off-by:
Bintian Wang <bintian.wang@huawei.com> Acked-by:
Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
- 19 Nov, 2014 6 commits
-
-
Hans de Goede authored
If CLK_MUX_INDEX_BIT is set, then each bit turns on / off a single parent, so theoretically multiple parents could be enabled at the same time, but in practice only one bit should ever be 1. So to select parent 0, set the register (*) to 0x01, to select parent 1 set it 0x02, parent 2, 0x04, parent 3, 0x08, etc. But the current code does: if (mux->flags & CLK_MUX_INDEX_BIT) index = (1 << ffs(index)); Which means that: For an input index of 0, ffs returns 0, so we set the register to 0x01, ok. For an input index of 1, ffs returns 1, so we set the register to 0x02, ok. For an input index of 2, ffs returns 2, so we set the register to 0x04, ok. For an input index of 3, ffs returns 1, so we set the register to 0x02, not good! The code should simply be: if (mux->flags & CLK_MUX_INDEX_BIT) index = 1 << index; Which always does the right thing, this commit fixes this. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
-
Geert Uytterhoeven authored
Commit 8e33f91a ("clk: shmobile: clk-mstp: change to using clock-indices") forgot to replace all occurrences of "renesas,clock-indices" in the driver-specific binding documentation. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
Michael Turquette authored
-
Zhen Lei authored
It's the same to the next statement, "ret = clk->parent". I think compiler will optimize it, it's just not looking well. Signed-off-by:
Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-
Michael Turquette authored
Merge tag 'v3.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next-rockchip - fixes for clock ordering/rate issues - do not keep all clocks enabled anymore - allow special pll rates for special cases
-
- 18 Nov, 2014 1 commit
-
-
Julien CHAUVEAU authored
The parent clock for hclk_lcdc1 was set to aclk_cpu instead of hclk_cpu. Signed-off-by:
Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
- 17 Nov, 2014 1 commit
-
-
Robert Jarzmik authored
Have each pxa variant (pxa25x, pxa27x, pxa3xx) have its own device-tree clock initializing function, to be able to register its own specific core clocks. Apply that change specifically to pxa27x. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
-