- 23 May, 2024 4 commits
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Jesse Zhang authored
Since the type of data_size is uint32_t, adev->umsch_mm.data_size - 1 >> 16 >> 16 is 0 regardless of the values of its operands So removing the operations upper_32_bits and lower_32_bits. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Jesse Zhang authored
When user space sets an invalid ta type, the pointer context will be empty. So it need to check the pointer context before using it Signed-off-by:
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Jesse Zhang authored
Enum asic_type always greater than or equal CHIP_TAHITI. Signed-off-by:
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Yang Wang authored
skip to create 'xxx_err_count' node when ACA is enabled. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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- 20 May, 2024 36 commits
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Tvrtko Ursulin authored
Align kerneldoc with the function argument name. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 26e20235 ("drm/amdgpu: Add amdgpu_bo_is_vm_bo helper") Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Dr. David Alan Gilbert authored
'dc_reg_sequence' was added in commit 44788bbc ("drm/amd/display: refactor reg_update") but isn't actually used. Remove it. Signed-off-by:
Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by:
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Dr. David Alan Gilbert authored
'aux_payloads' is unused since commit eae5ffa9 ("drm/amd/display: Switch ddc to new aux interface") Remove it. Signed-off-by:
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Dr. David Alan Gilbert authored
'hqd_registers' used to be used in a member of the 'bonaire_mqd' struct. 'bonaire_mqd' was removed by commit 486d807c ("drm/amdgpu: remove duplicate definition of cik_mqd") It's now unused. Remove 'hqd_registers' as well. Signed-off-by:
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Kenneth Feng authored
enable thermal alert on smu 14.0.2/3 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Kenneth Feng authored
add thm 14.0.2 header file v2: add license, update to latest changes (Alex) Signed-off-by:
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Asad Kamal authored
Remove gpu_metrics_v1_6 temporarily until tool support is ready This reverts commit 00dedab0. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Lijo Lazar authored
Add documentation about the newly added pm_policy node in sysfs. Signed-off-by:
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Asad Kamal authored
Remove gpu_metrics_v1_6 usage for SMUv13.0.6 temporarily and use gpu_metrics_v1_5 until tool support is ready for it. This reverts commit 74ab6253. Signed-off-by:
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Lijo Lazar authored
Remove unused callback to set PLPD policy and its implementation from arcturus, aldebaran and SMUv13.0.6 SOCs. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Tao Zhou authored
Avoid overflow issue. Signed-off-by:
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Li Ma authored
MinGfxClk in Dpmclocks_t is wrong. According to pmfw, dropping an uint8_t spare in Dpmclocks_t. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Victor Skvortsov authored
The guest recovery sequence is buggy in Fatal Error when both FLR & KFD reset workitems are queued at the same time. In addition, FLR guest recovery sequence is out of order when PF/VF communication breaks due to a GPU fatal error As a temporary work around, perform a KFD style reset (Initiate reset request from the guest) inside the pf2vf thread on FED. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
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Victor Skvortsov authored
Runtime KIQ interface to read/write registers in VF may take longer than expected for BM environment. Extend the timeout. Signed-off-by:
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Aric Cyr authored
This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316, dcn35/351, dcn401 and brings along the following: - Fix powerpc compilation - Fix TBT+TypeC Daisy-chain lightup - Fix ODM combine setup - Fix OTC underflow on dcn35 - Fix DVI config for dcn401 - Add ips status info to debugfs - Add 3DLUT DMA load trigger - Modify clock programming to support DPM - Disable dcn401 idle optimizations Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Roman Li authored
[Why] Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP: "undefined reference to `dc_bandwidth_in_kbps_from_timing'" [How] Fix Makefile to move dsc files out of DC_FP guard. Fixes: 00c39110 ("drm/amd/display: Add misc DC changes for DCN401") Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Cruise authored
[Why] When the link BW is smaller than the request BW, the DP LT just kept running and fallback to lower link config. DP LT just aborted if is_hpd_pending bit is high. But is_hpd_pending bit indicates a new HPD event received. It doesn't mean the HPD is low. [How] Abort the DP LT if the link BW is smaller than the request BW. Remove checking is_hpd_pending bit in DP LT. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Cruise <cruise.hung@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] At the time of block sequence construction, the exact reference DPP/DISP clock is not yet known, so the clock should be passed by reference to the DTO programming function. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] Disable to improve stability for now. Reviewed-by:
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Alvin Lee authored
[Description] There is a corner case where we're in an ODM config that has recout.x != 0. In these scenarios we have to take into account the extra offset in the ODM adjustment for cursor. Reviewed-by:
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Wenjing Liu authored
[why] A recent change for ODM combine refactor contains a typo which causes ODM combine mode programmed incorrectly. Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
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Roman Li authored
[Why] Disable idle optimization for each atomic commit is unnecessary, and can lead to a potential race condition. [How] Remove idle optimization check from amdgpu_dm_atomic_commit_tail() Fixes: 196107eb ("drm/amd/display: Add IPS checks before dcn register access") Cc: stable@vger.kernel.org Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
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Nicholas Susanto authored
[Why] Missing check for when there is new pipe configuration but both cur_pipe and new_pipe are both populated causing update_state of DSC for that instance not being updated correctly. This causes some display mode changes to cause underflow since DSCCLK is still gated when the display requires DSC. [How] Added another condition in the new pipe addition branch that checks if there is a new pipe configuration and if it is not the same as cur_pipe. cur_pipe does not necessarily have to be NULL to go in this branch. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Roman Li authored
[Why] For debugging and testing purposes. [How] If IPS is supported create ips_status debugfs entry. Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status Reviewed-by:
Jerry Zuo <jerry.zuo@amd.com> Acked-by:
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Roman Li authored
[Why] Reset the shared dmub firmware region on dmub hw init to start with known state. [How] Memset the shared region to 0 in dmub_hw_init(). Suggested-by:
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Ilya Bakoulin authored
[Why/How] Need to be able to trigger a DMA load to update 3DLUT contents in MPC. Adding a HWSS function to serve as the trigger. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Chris Park authored
[Why] DML 2.1 allocates two types of memory in its ctx structure but does not destroy them, causing memory leak whenever DML 2.1 instance is created and destroyed. [How] Deallocate two instances of allocated memory whenever DML 2.1 is destroyed. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Chris Park <chris.park@amd.com> Tested-by:
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Hersen Wu authored
[Why] Coverity reports NULL_RETURN warning. [How] Add pointer NULL check. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Kenneth Feng authored
update driver-if interface for smu 14.0.2/3 Signed-off-by:
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Rodrigo Siqueira authored
Acked-by:
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Dillon Varone authored
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to hardware guidance. Reviewed-by:
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Harikrishna Revalla authored
[why] Cleaning up the code refactor requires hubbub to be in its own component. [how] Move all DCN401 files under newly created hubbub folder and fixing the makefiles. Reviewed-by:
Harikrishna Revalla <Harikrishna.Revalla@amd.com> Tested-by:
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Samson Tam authored
[Why] Enable adaptive scaler support for DCN401 [How] - Enable build flag for SPL - Set prefer_easf flag to true - Apply light linear scaling policy based on transfer function and pixel format. Choose between linear or non-linear scaling - Set matrix_mode based on pixel format - Disable ring estimator - Add missing EASF register defines, masks, and writes - Disable EASF if scale ratio or number of taps is unsupported and when bypassing the scaler - Add debug flags and registry keys for debugging SPL and EASF - Add support for Visual Confirm with EASF Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Alex Hung authored
This fixes indentations and adjust spaces for better readability and code styles. Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Chris Park authored
[Why] DVI is TMDS signal like HDMI but without audio. Current signal check does not correctly reflect DVI clock programming. [How] Define a new signal check for TMDS that includes DVI to HDMI TMDS programming. Reviewed-by:
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Alex Hung authored
The comparisons intend to be DCN401 inclusive, and fix it by adding equal signs. Reviewed-by:
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