1. 10 Sep, 2020 28 commits
  2. 09 Sep, 2020 12 commits
    • Florian Fainelli's avatar
      net: dsa: b53: Report VLAN table occupancy via devlink · 4f6a5caf
      Florian Fainelli authored
      We already maintain an array of VLANs used by the switch so we can
      simply iterate over it to report the occupancy via devlink.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4f6a5caf
    • David S. Miller's avatar
      Merge branch 'Marvell-PP2-2-PTP-support' · 4a056990
      David S. Miller authored
      Russell King says:
      
      ====================
      Marvell PP2.2 PTP support
      
      This series adds PTP support for PP2.2 hardware to the mvpp2 driver.
      Tested on the Macchiatobin eth1 port.
      
      Note that on the Macchiatobin, eth0 uses a separate TAI block from
      eth1, and there is no hardware synchronisation between the two.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4a056990
    • Russell King's avatar
      net: mvpp2: ptp: add support for transmit timestamping · f5015a59
      Russell King authored
      Add support for timestamping transmit packets.  We allocate SYNC
      messages to queue 1, every other message to queue 0.
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f5015a59
    • Russell King's avatar
      net: mvpp2: ptp: add support for receive timestamping · ce3497e2
      Russell King authored
      Add support for receive timestamping. When enabled, the hardware adds
      a timestamp into the receive queue descriptor for all received packets
      with no filtering. Hence, we can only support NONE or ALL receive
      filter modes.
      
      The timestamp in the receive queue contains two bit sof seconds and
      the full nanosecond timestamp. This has to be merged with the remainder
      of the seconds from the TAI clock to arrive at a full timestamp before
      we can convert it to a ktime for the skb hardware timestamp field.
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Acked-by: default avatarRichard Cochran <richardcochran@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ce3497e2
    • Russell King's avatar
      net: mvpp2: ptp: add TAI support · 91dd7195
      Russell King authored
      Add support for the TAI block in the mvpp2.2 hardware.
      Acked-by: default avatarRichard Cochran <richardcochran@gmail.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      91dd7195
    • Russell King's avatar
      net: mvpp2: check first level interrupt status registers · b4b17714
      Russell King authored
      Check the first level interrupt status registers to determine how to
      further process the port interrupt. We will need this to know whether
      to invoke the link status processing and/or the PTP processing for
      both XLG and GMAC.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b4b17714
    • Russell King's avatar
      net: mvpp2: rename mis-named "link status" interrupt · 89141972
      Russell King authored
      The link interrupt is used for way more than just the link status; it
      comes from a collection of units to do with the port. The Marvell
      documentation describes the interrupt as "GOP port X interrupt".
      
      Since we are adding PTP support, and the PTP interrupt uses this,
      rename it to be more inline with the documentation.
      
      This interrupt is also mis-named in the DT binding, but we leave that
      alone.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      89141972
    • Russell King's avatar
      net: mvpp2: restructure "link status" interrupt handling · 36cfd3a6
      Russell King authored
      The "link status" interrupt is used for more than just link status.
      Restructure mvpp2_link_status_isr() so we can add additional handling.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      36cfd3a6
    • David S. Miller's avatar
      Merge branch 'devlink-show-controller-number' · b599a5b9
      David S. Miller authored
      Parav Pandit says:
      
      ====================
      devlink show controller number
      
      Currently a devlink instance that supports an eswitch handles eswitch
      ports of two type of controllers.
      (1) controller discovered on same system where eswitch resides.
      This is the case where PCI PF/VF of a controller and devlink eswitch
      instance both are located on a single system.
      (2) controller located on external system.
      This is the case where a controller is plugged in one system and its
      devlink eswitch ports are located in a different system. In this case
      devlink instance of the eswitch only have access to ports of the
      controller.
      However, there is no way to describe that a eswitch devlink port
      belongs to which controller (mainly which external host controller).
      This problem is more prevalent when port attribute such as PF and VF
      numbers are overlapping between multiple controllers of same eswitch.
      Due to this, for a specific switch_id, unique phys_port_name cannot
      be constructed for such devlink ports.
      
      This short series overcomes this limitation by defining two new
      attributes.
      (a) external: Indicates if port belongs to external controller
      (b) controller number: Indicates a controller number of the port
      
      Based on this a unique phys_port_name is prepared using controller
      number.
      
      phys_port_name construction using unique controller number is only
      applicable to external controller ports. This ensures that for
      non smartnic usecases where there is no external controller,
      phys_port_name stays same as before.
      
      Patch summary:
      Patch-1 Added mlx5 driver to read controller number
      Patch-2 Adds the missing comment for the port attributes
      Patch-3 Move structure comments away from structure fields
      Patch-4 external attribute added for PCI port flavours
      Patch-5 Add controller number
      Patch-6 Use controller number to build phys_port_name
      
      ---
      Changelog:
      v2->v3:
       - Updated diagram to get rid of controller 'A' and 'B'
       - Kept ports of single controller together in diagram
       - Updated diagram for pf1's VF and SF and its ports
      v1->v2:
       - Added text diagram of multiple controllers
       - Updated example for a VF
       - Addressed comments from Jiri and Jakub
       - Moved controller number attribute to PCI port flavours
         This enables to better, hirerchical view with controller and its
          PF, VF numbers
       - Split 'external' and 'controller number' attributes as two
         different attributes
       - Merged mlx5_core driver to avoid compiliation break
      ====================
      Acked-by: default avatarJakub Kicinski <kuba@kernel.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b599a5b9
    • Parav Pandit's avatar
      devlink: Use controller while building phys_port_name · 66b17082
      Parav Pandit authored
      Now that controller number attribute is available, use it when
      building phsy_port_name for external controller ports.
      
      An example devlink port and representor netdev name consist of controller
      annotation for external controller with controller number = 1,
      for a VF 1 of PF 0:
      
      $ devlink port show pci/0000:06:00.0/2
      pci/0000:06:00.0/2: type eth netdev ens2f0c1pf0vf1 flavour pcivf controller 1 pfnum 0 vfnum 1 external true splittable false
        function:
          hw_addr 00:00:00:00:00:00
      
      $ devlink port show pci/0000:06:00.0/2 -jp
      {
          "port": {
              "pci/0000:06:00.0/2": {
                  "type": "eth",
                  "netdev": "ens2f0c1pf0vf1",
                  "flavour": "pcivf",
                  "controller": 1,
                  "pfnum": 0,
                  "vfnum": 1,
                  "external": true,
                  "splittable": false,
                  "function": {
                      "hw_addr": "00:00:00:00:00:00"
                  }
              }
          }
      }
      
      Controller number annotation is skipped for non external controllers to
      maintain backward compatibility.
      Signed-off-by: default avatarParav Pandit <parav@nvidia.com>
      Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      66b17082
    • Parav Pandit's avatar
      devlink: Introduce controller number · 3a2d9588
      Parav Pandit authored
      A devlink port may be for a controller consist of PCI device.
      A devlink instance holds ports of two types of controllers.
      (1) controller discovered on same system where eswitch resides
      This is the case where PCI PF/VF of a controller and devlink eswitch
      instance both are located on a single system.
      (2) controller located on external host system.
      This is the case where a controller is located in one system and its
      devlink eswitch ports are located in a different system.
      
      When a devlink eswitch instance serves the devlink ports of both
      controllers together, PCI PF/VF numbers may overlap.
      Due to this a unique phys_port_name cannot be constructed.
      
      For example in below such system controller-0 and controller-1, each has
      PCI PF pf0 whose eswitch ports can be present in controller-0.
      These results in phys_port_name as "pf0" for both.
      Similar problem exists for VFs and upcoming Sub functions.
      
      An example view of two controller systems:
      
                   ---------------------------------------------------------
                   |                                                       |
                   |           --------- ---------         ------- ------- |
      -----------  |           | vf(s) | | sf(s) |         |vf(s)| |sf(s)| |
      | server  |  | -------   ----/---- ---/----- ------- ---/--- ---/--- |
      | pci rc  |=== | pf0 |______/________/       | pf1 |___/_______/     |
      | connect |  | -------                       -------                 |
      -----------  |     | controller_num=1 (no eswitch)                   |
                   ------|--------------------------------------------------
                   (internal wire)
                         |
                   ---------------------------------------------------------
                   | devlink eswitch ports and reps                        |
                   | ----------------------------------------------------- |
                   | |ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 |ctrl-0 | |
                   | |pf0    | pf0vfN | pf0sfN | pf1    | pf1vfN |pf1sfN | |
                   | ----------------------------------------------------- |
                   | |ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 |ctrl-1 | |
                   | |pf1    | pf1vfN | pf1sfN | pf1    | pf1vfN |pf0sfN | |
                   | ----------------------------------------------------- |
                   |                                                       |
                   |                                                       |
                   |           --------- ---------         ------- ------- |
                   |           | vf(s) | | sf(s) |         |vf(s)| |sf(s)| |
                   | -------   ----/---- ---/----- ------- ---/--- ---/--- |
                   | | pf0 |______/________/       | pf1 |___/_______/     |
                   | -------                       -------                 |
                   |                                                       |
                   |  local controller_num=0 (eswitch)                     |
                   ---------------------------------------------------------
      
      An example devlink port for external controller with controller
      number = 1 for a VF 1 of PF 0:
      
      $ devlink port show pci/0000:06:00.0/2
      pci/0000:06:00.0/2: type eth netdev ens2f0pf0vf1 flavour pcivf controller 1 pfnum 0 vfnum 1 external true splittable false
        function:
          hw_addr 00:00:00:00:00:00
      
      $ devlink port show pci/0000:06:00.0/2 -jp
      {
          "port": {
              "pci/0000:06:00.0/2": {
                  "type": "eth",
                  "netdev": "ens2f0pf0vf1",
                  "flavour": "pcivf",
                  "controller": 1,
                  "pfnum": 0,
                  "vfnum": 1,
                  "external": true,
                  "splittable": false,
                  "function": {
                      "hw_addr": "00:00:00:00:00:00"
                  }
              }
          }
      }
      Signed-off-by: default avatarParav Pandit <parav@nvidia.com>
      Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      3a2d9588
    • Parav Pandit's avatar
      devlink: Introduce external controller flag · 05b595e9
      Parav Pandit authored
      A devlink eswitch port may represent PCI PF/VF ports of a controller.
      
      A controller either located on same system or it can be an external
      controller located in host where such NIC is plugged in.
      
      Add the ability for driver to specify if a port is for external
      controller.
      
      Use such flag in the mlx5_core driver.
      
      An example of an external controller having VF1 of PF0 belong to
      controller 1.
      
      $ devlink port show pci/0000:06:00.0/2
      pci/0000:06:00.0/2: type eth netdev ens2f0pf0vf1 flavour pcivf pfnum 0 vfnum 1 external true splittable false
        function:
          hw_addr 00:00:00:00:00:00
      $ devlink port show pci/0000:06:00.0/2 -jp
      {
          "port": {
              "pci/0000:06:00.0/2": {
                  "type": "eth",
                  "netdev": "ens2f0pf0vf1",
                  "flavour": "pcivf",
                  "pfnum": 0,
                  "vfnum": 1,
                  "external": true,
                  "splittable": false,
                  "function": {
                      "hw_addr": "00:00:00:00:00:00"
                  }
              }
          }
      }
      Signed-off-by: default avatarParav Pandit <parav@nvidia.com>
      Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      05b595e9