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  1. 12 Jan, 2010 4 commits
    • Paul Mundt's avatar
      sh64: Fix up early serial fixmap. · 65fedbbe
      Paul Mundt authored 
      This was conditionalized on CONFIG_EARLY_PRINTK, which has subsequently
gone away. Now that the serial driver always supports the early console,
make sure we always establish the mapping.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      65fedbbe
    • Paul Mundt's avatar
      sh: Tidy up the sh bios VBR handling. · 191d0d24
      Paul Mundt authored 
      This moves the VBR handling out of the main trap handling code and in to
the sh-bios helper code. A couple of accessors are added in order to
permit other kernel code to get at the VBR value for state save/restore
paths.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      191d0d24
    • Paul Mundt's avatar
      sh: default to sparseirq. · ee2760ea
      Paul Mundt authored 
      As SH has a very sparse IRQ map by default, all new CPUs and boards
benefit from using sparseirq by default. Despite this, there are still a
few stragglers (mostly due to using a fixed IRQ range for their FPGA
IRQ mappings), and these still need to be converted over one by one. As
these are now in the minority, and we do not want to encourage this sort
of brain-damage in newer board ports, we force sparseirq on.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      ee2760ea
    • Paul Mundt's avatar
      sh: mach-se: Convert SE7343 FPGA to dynamic IRQ allocation. · 53e6d8e0
      Paul Mundt authored 
      This gets rid of the arbitrary set of vectors used by the SE7722 FPGA
interrupt controller and switches over to a completely dynamic set.
No assumptions regarding a contiguous range are made, and the platform
resources themselves need to be filled in lazily.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      53e6d8e0
  3. 08 Jan, 2010 1 commit
    • Paul Mundt's avatar
      sh: consolidate atomic_cmpxchg()/atomic_add_unless() definitions. · 8c0b8139
      Paul Mundt authored 
      The LL/SC and IRQ versions were using generic stubs while the GRB version
was just reimplementing what it already had for the standard cmpxchg()
code. As we have optimized cmpxchg() implementations that are decoupled
from the atomic code, simply falling back on the generic wrapper does the
right thing. With this in place the GRB case is unaffected while the
LL/SC case gets to use its optimized cmpxchg().
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      8c0b8139
  5. 06 Jan, 2010 1 commit
  7. 05 Jan, 2010 2 commits
  9. 04 Jan, 2010 5 commits
  11. 02 Jan, 2010 3 commits
    • Matt Fleming's avatar
      sh: Move page table allocation out of line · 2a5eacca
      Matt Fleming authored 
      We also switched away from quicklists and instead moved to slab
caches. After benchmarking both implementations the difference is
negligible. The slab caches suit us better though because the size of a
pgd table is just 4 entries when we're using a 3-level page table layout
and quicklists always deal with pages.
Signed-off-by: default avatarMatt Fleming <matt@console-pimps.org>
      2a5eacca
    • Matt Fleming's avatar
      sh: Optimise flush_dcache_page() on SH4 · b4c89276
      Matt Fleming authored 
      If the page is not mapped into any process's address space then aliases
cannot exist in the cache. So reduce the amount of flushing we perform.
Signed-off-by: default avatarMatt Fleming <matt@console-pimps.org>
      b4c89276
    • Matt Fleming's avatar
      sh: Correct the PTRS_PER_PMD and PMD_SHIFT values · 3f5ab768
      Matt Fleming authored 
      The previous expressions were wrong which made free_pmd_range() explode
when using anything other than 4KB pages (which is why 8KB and 64KB
pages were disabled with the 3-level page table layout).

The problem was that pmd_offset() was returning an index of non-zero
when it should have been returning 0. This non-zero offset was used to
calculate the address of the pmd table to free in free_pmd_range(),
which ended up trying to free an object that was not aligned on a page
boundary.

Now 3-level page tables should work with 4KB, 8KB and 64KB pages.
Signed-off-by: default avatarMatt Fleming <matt@console-pimps.org>
      3f5ab768
  13. 31 Dec, 2009 1 commit
  15. 29 Dec, 2009 1 commit
    • Paul Mundt's avatar
      sh: Only provide a PCLK definition for legacy CPG CPUs. · 8152a74b
      Paul Mundt authored 
      As CPUs are migrated over to more fully-featured clock frameworks of
their own and off of the legacy CPG code, they no longer have any real
need for defining the PCLK value. The PCLK define in itself is already
fairly misleading, as many boards get their input clocks from different
sources, making this value fairly arbitrary anyways.

Outside of the legacy CPG clock framework, the only place where this
value is used is for deriving CLOCK_TICK_RATE, which we set back to the
legacy PIT value that it was before the PCLK definitions were added in
the first place.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      8152a74b
  17. 24 Dec, 2009 22 commits
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