- 12 Apr, 2022 8 commits
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Duncan Ma authored
[WHY] Implement changes to transition from Pre-OS odm to Post-OS odm support. Seamless boot case is also considered. [HOW] Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has odm enabled. Reset odm and det size when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Duncan Ma <Duncan.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Oliver Logush authored
[why] Need to update the update_clock sequence to a fully tested sequence for dcn30 [how] Removed the check to see if clock is lowered Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Oliver Logush <oliver.logush@amd.com> Signed-off-by:
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Oliver Logush authored
[why] Make sure smu is not busy before sending another request, this is to prevent stress failures from MS. [how] Check to make sure the SMU fw busy signal is cleared before sending another request Reviewed-by:
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Paul Hsieh authored
[WHY] In headless systems, if SetMode/Power down timer is not called, hardware will not be powered down causing HW/SW discrepancies. Powering down hardware on SetPowerState to D3 will ensure SW/HW state is accurate. [HOW] 1. If PowerDownThread timer is not trigger but OS call SetPowerState to D3, power down hardware. 2. Update HDMI hang w/a to apply to all TMDS signals on headless system Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Paul Hsieh <paul.hsieh@amd.com> Signed-off-by:
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Charlene Liu authored
[why] dcn316's dtbclk is from non_ss clock source. no compensation required here. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Evgenii Krasnikov authored
[HOW&WHY] Make sure psr_force_static() can always be called regardless of psr_allow_active value. Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Reviewed-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Reviewed-by:
Nicholas Choi <Nicholas.Choi@amd.com> Acked-by:
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Harry VanZyllDeJong authored
[HOW&WHY] VRR was getting set at the same time the timing generator would be null when there was no display connected. Added null check to the timing generator variable so it does not get referenced if it is null. Reviewed-by:
Harry VanZyllDeJong <hvanzyll@amd.com> Signed-off-by:
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Iswara Nagulendran authored
[WHY] Screen was seen corrupted for a few ms when switching both ways. There was also not enough bandwidth for HDR to be enabled in HG disabled mode. This was due to FEC being enabled although DSC was not supported or disabled for the EDP. [HOW] Check for EDP DSC support in DC caps or if DSC should be disabled for EDP before enabling FEC for EDP. Reviewed-by:
Iswara Nagulendran <inagulen@amd.com> Signed-off-by:
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- 11 Apr, 2022 13 commits
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Tom Rix authored
The only use of the global variables in r600_blit_shaders.c were in the old drivers/gpu/drm/radeon/r600_blit.c This file was removed in commit 8333f607 ("drm/radeon: remove UMS support") So remove the r600_blit_shaders.[c|h] files Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Max Erenberg authored
[WHY] The dGPU cannot enter PSR when it is not connected to a panel. [HOW] Added a check to dc_link_set_psr_allow_active which returns early if panel is disconnected. Reviewed-by:
Max Erenberg <merenber@amd.com> Signed-off-by:
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Saaem Rizvi authored
[WHY] Z10 is should not be enabled by default on DCN31. [HOW] Using DC debug flags to disable Z10 by default on DCN31. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Saaem Rizvi <syerizvi@amd.com> Signed-off-by:
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Josip Pavic authored
[Why] When booting, the driver waits for the MPC idle bit to be set as part of pipe initialization. However, on some systems this occurs before OTG is enabled, and since the MPC idle bit won't be set until the vupdate signal occurs (which requires OTG to be enabled), this never happens and the wait times out. This can add hundreds of milliseconds to the boot time. [How] Do not wait for mpc idle if tg is disabled Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
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Eric Yang authored
[Why] Z10 and S0i3 have some shared path. Previous code clean up , incorrectly removed these pointers, which breaks s0i3 restore [How] Do not clear the function pointers based on Z10 disable. Reviewed-by:
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Stanley.Yang authored
In order to debug ras error, driver will print IPID/SYND/MISC0 register value if detect correctable or uncorrectable error. Provide umc_query_error_status_helper function to reduce code redundancy. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Use div_u64() rather than a a 64 bit divide. Fixes: 3fe5739d ("drm/amd/display: Add flip interval workaround") Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Grigory Vasilyev authored
Instead of the 'amdgpu_ring_priority_level' type, the 'amdgpu_gfx_pipe_priority' type was used, which is an error when setting ring priority. This is a minor error, but may cause problems in the future. Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3, but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the code. Signed-off-by:
Grigory Vasilyev <h0tc0d3@gmail.com> Signed-off-by:
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Tom Rix authored
cayman_default_state and cayman_default_size are only used in ni.c. Single file symbols should be static. So move their definitions to cayman_blit_shaders.h and change their storage-class-specifier to static. Remove unneeded cayman_blit_shader.c cayman_ps/vs definitions were removed with commit 4f862967 ("drm/radeon/kms: remove r6xx+ blit copy routines") So their declarations in cayman_blit_shader.h are not needed, so remove them. Signed-off-by:
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Tom St Denis authored
The data revision was not changed to 5 from 4 when the CG flags were extended to 64-bits. Since this was missed I took the opportunity to add future upper 64-bits of PG flags as well so we don't need to bump it again when that comes. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Yongqiang Sun authored
Add CONFIG_X86 check to fix the build error. Fixes: 49aa98ca ("drm/amd/amdgpu: Only reserve vram for firmware with vega9 MS_HYPERV host.") Reported-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Philip Yang authored
Application could change XNACK enabled to disabled while KFD is draining stale retry fault, therefore the check for whether to drain retry faults must be before the check for whether xnack_enabled, to avoid report incorrect vm fault after application changes XNACK mode. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Lijo Lazar authored
Use flexible array member in ip discovery struct as recommended[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays v2: squash in struct_size fixes Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 08 Apr, 2022 1 commit
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Evan Quan authored
With this, we can support more CG flags. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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- 07 Apr, 2022 8 commits
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Yongqiang Sun authored
driver loading failed on VEGA10 SRIOV VF with linux host due to a wide range of stolen reserved vram. Since VEGA10 SRIOV VF need to reserve vram for firmware with windows Hyper_V host specifically, check hypervisor type to only reserve memory for it, and the range of the reserved vram can be limited to between 5M-7M area. Fixes: faad5cca ("drm/amdgpu: Add stolen reserved memory for MI25 SRIOV.") Signed-off-by:
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Felix Kuehling authored
Check that adev->gfx.ras is valid before using it. Fixes: 6475ae2b ("drm/amdgpu: add UTCL2 RAS poison query for Aldebaran (v2)") CC: Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Tom Rix authored
Smatch reports this issue hdcp1_execution.c:500:29: warning: function 'mod_hdcp_hdcp1_dp_execution' with external linkage has definition The storage-class-specifier extern is not needed in a definition, so remove it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Tomasz Moń authored
Enabling gfxoff quirk results in perfectly usable graphical user interface on MacBook Pro (15-inch, 2019) with Radeon Pro Vega 20 4 GB. Without the quirk, X server is completely unusable as every few seconds there is gpu reset due to ring gfx timeout. Signed-off-by:
Tomasz Moń <desowin@gmail.com> Signed-off-by:
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Kai-Heng Feng authored
DP/HDMI audio on AMD PRO VII stops working after S3: [ 149.450391] amdgpu 0000:63:00.0: amdgpu: MODE1 reset [ 149.450395] amdgpu 0000:63:00.0: amdgpu: GPU mode1 reset [ 149.450494] amdgpu 0000:63:00.0: amdgpu: GPU psp mode1 reset [ 149.983693] snd_hda_intel 0000:63:00.1: refused to change power state from D0 to D3hot [ 150.003439] amdgpu 0000:63:00.0: refused to change power state from D0 to D3hot ... [ 155.432975] snd_hda_intel 0000:63:00.1: CORB reset timeout#2, CORBRP = 65535 The offending commit is daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)"). Commit 34452ac3 ("drm/amdgpu: don't use BACO for reset in S3 ") doesn't help, so the issue is something different. Assuming that to make HDA resume to D0 fully realized, it needs to be successfully put to D3 first. And this guesswork proves working, by moving amdgpu_asic_reset() to noirq callback, so it's called after HDA function is in D3. Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Alex Deucher authored
Drop the trailing vcn. Fixes: afc2f276 ("drm/amdgpu/vcn: add vcn support for vcn 3.1.2") Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Melissa Wen authored
"Pre-multiplied" is the default pixel blend mode for KMS/DRM, as documented in supported_modes of drm_plane_create_blend_mode_property(): https://cgit.freedesktop.org/drm/drm-misc/tree/drivers/gpu/drm/drm_blend.c In this mode, both 'pixel alpha' and 'plane alpha' participate in the calculation, as described by the pixel blend mode formula in KMS/DRM documentation: out.rgb = plane_alpha * fg.rgb + (1 - (plane_alpha * fg.alpha)) * bg.rgb Considering the blend config mechanisms we have in the driver so far, the alpha mode that better fits this blend mode is the _PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, where the value for global_gain is the plane alpha (global_alpha). With this change, alpha property stops to be ignored. It also addresses Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1734 v2: * keep the 8-bit value for global_alpha_value (Nicholas) * correct the logical ordering for combined global gain (Nicholas) * apply to dcn10 too (Nicholas) Signed-off-by:
Melissa Wen <mwen@igalia.com> Tested-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Simon Ser <contact@emersion.fr> Signed-off-by:
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Felix Kuehling authored
Use rcu_read_lock to read p->event_idr concurrently with other readers and writers. Use p->event_mutex only for creating and destroying events and in kfd_wait_on_events. Protect the contents of the kfd_event structure with a per-event spinlock that can be taken inside the rcu_read_lock critical section. This eliminates contention of p->event_mutex in set_event, which tends to be on the critical path for dispatch latency even when busy waiting is used. It also eliminates lock contention in event interrupt handlers. Since the p->event_mutex is now used much less, the impact of requiring it in kfd_wait_on_events should also be much smaller. This should improve event handling latency for processes using multiple GPUs concurrently. v2: Reschedule the worker periodically to avoid soft lockup warnings Signed-off-by:
Sanjay Tripathi <sanjay.tripathi@amd.com> Signed-off-by:
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- 06 Apr, 2022 8 commits
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Lv Ruyi authored
'dm_services.h' included in 'freesync,c' is duplicated, so remove one. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Signed-off-by:
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Alex Deucher authored
SMU takes clock limits in Mhz units. socclk and fclk were using 10 khz units in some cases. Switch to Mhz units. Fixes higher than required SoC clocks. Fixes: 97cf3299 ("drm/amd/pm: Removed fixed clock in auto mode DPM") Reviewed-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
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Dmytro Laktyushkin authored
[Why & How] Make dcn315 base its clock table off dcfclk rather than fclk. This change also adds some sanity checking to make sure an empty pmfw table does not result in invalid dal clocks. Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Grigory Vasilyev authored
Variable igp_lane_info always is 0. 0 & any value = 0 and false. In this way, all сonditional statements will false. The code was leftover from when the code was ported from radeon where igp_lane_info was derived from the vbios on supported platforms. [update commit message - Alex] Signed-off-by:
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Tom Rix authored
Smatch reports these issues si_blit_shaders.c:31:11: warning: symbol 'si_default_state' was not declared. Should it be static? si_blit_shaders.c:253:11: warning: symbol 'si_default_size' was not declared. Should it be static? Both symbols are only used in si.c. Single file symbols should be static. So move the definition of si_default_state and si_default_size to si_blit_shader.h and change their storage-class-specifier to static. Remove unneeded si_blit_shader.c Reviewed-by:
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Benjamin Marty authored
Fixes crash on MST Hub disconnect. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1849 Fixes: ee2698cf ("drm/amd/display: Changed pipe split policy to allow for multi-display pipe split") Signed-off-by:
Benjamin Marty <info@benjaminmarty.ch> Signed-off-by:
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Guo Zhengkui authored
Replace `if (!ret)` with `else` for simplification. Signed-off-by:
Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by:
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Philip Yang authored
bo_adev is NULL for system memory mapping to GPU. Fixes: 30671b44 ("drm/amdgpu: fix TLB flushing during eviction") Signed-off-by:
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- 05 Apr, 2022 2 commits
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Anthony Koo authored
- Add options to allow for configurable PHY options during PSR active state - Remove unused versioning and git hash Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] Function to calculate scaling ratios can be called with invalid plane src/dest, causing a divide by zero. [HOW] Fail building scaling params if plane state src/dest rects are unpopulated Tested-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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