- 20 Nov, 2020 10 commits
-
-
Giovanni Cabiddu authored
Add an hook to initialize the vector routing table with the default values before MSIx is enabled. The new function set_msix_rttable() is called only if present in the struct adf_hw_device_data of the device. This is to allow for QAT devices that do not support that functionality. Signed-off-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by:
Fiona Trahe <fiona.trahe@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Giovanni Cabiddu authored
Introduce support for devices that require multiple firmware images. If a device requires more than a firmware image to operate, load the image to the appropriate Acceleration Engine (AE). Signed-off-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by:
Fiona Trahe <fiona.trahe@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Zhang Qilong authored
The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: f7b2b5dd ("crypto: omap-aes - add error check for pm_runtime_get_sync") Signed-off-by:
Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Yang Shen authored
The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs' set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the thread which is sending request, the throughput will be just half. So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work on some different CPUS. Signed-off-by:
Yang Shen <shenyang39@huawei.com> Reviewed-by:
Zaibo Xu <xuzaibo@huawei.com> Reviewed-by:
Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Herbert Xu authored
This patch moves the curve25519_selftest into curve25519.h so we don't get a warning from gcc complaining about a missing prototype. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Eric Biggers authored
Currently <crypto/sha.h> contains declarations for both SHA-1 and SHA-2, and <crypto/sha3.h> contains declarations for SHA-3. This organization is inconsistent, but more importantly SHA-1 is no longer considered to be cryptographically secure. So to the extent possible, SHA-1 shouldn't be grouped together with any of the other SHA versions, and usage of it should be phased out. Therefore, split <crypto/sha.h> into two headers <crypto/sha1.h> and <crypto/sha2.h>, and make everyone explicitly specify whether they want the declarations for SHA-1, SHA-2, or both. This avoids making the SHA-1 declarations visible to files that don't want anything to do with SHA-1. It also prepares for potentially moving sha1.h into a new insecure/ or dangerous/ directory. Signed-off-by:
Eric Biggers <ebiggers@google.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Acked-by:
Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Nathan Chancellor authored
Clang warns: drivers/crypto/amcc/crypto4xx_core.c:921:60: warning: operator '?:' has lower precedence than '|'; '|' will be evaluated first [-Wbitwise-conditional-parentheses] (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ drivers/crypto/amcc/crypto4xx_core.c:921:60: note: place parentheses around the '|' expression to silence this warning (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ? ^ ) drivers/crypto/amcc/crypto4xx_core.c:921:60: note: place parentheses around the '?:' expression to evaluate it first (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ? ^ ( 1 warning generated. It looks like this should have been a logical OR so that PD_CTL_HASH_FINAL gets added to the w bitmask if crypto_tfm_alg_type is either CRYPTO_ALG_TYPE_AHASH or CRYPTO_ALG_TYPE_AEAD. Change the operator so that everything works properly. Fixes: 4b5b7999 ("crypto: crypto4xx - fix stalls under heavy load") Link: https://github.com/ClangBuiltLinux/linux/issues/1198Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Reviewed-by:
Christian Lamparter <chunkeey@gmail.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Horia Geantă authored
Wang Qing reports that IS_ERR_OR_NULL() should be matched with PTR_ERR_OR_ZERO(), not PTR_ERR(). As it turns out, the error path always returns an error code, i.e. NULL is never returned. Update the code accordingly - s/IS_ERR_OR_NULL/IS_ERR. Reported-by:
Wang Qing <wangqing@vivo.com> Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Ard Biesheuvel authored
Instead of copying the calculated authentication tag to memory and calling crypto_memneq() to verify it, use vector bytewise compare and min across vector instructions to decide whether the tag is valid. This is more efficient, and given that the tag is only transiently held in a NEON register, it is also safer, given that calculated tags for failed decryptions should be withheld. Signed-off-by:
Ard Biesheuvel <ardb@kernel.org> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Kai Ye authored
Fix aead auth setting key process error. if use soft shash function, driver need to use digest size replace of the user input key length. Signed-off-by:
Kai Ye <yekai13@huawei.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
- 13 Nov, 2020 30 commits
-
-
Ard Biesheuvel authored
Based on lessons learnt from optimizing the 32-bit version of this driver, we can simplify the arm64 version considerably, by reordering the final two stores when the last block is not a multiple of 64 bytes. This removes the need to use permutation instructions to calculate the elements that are clobbered by the final overlapping store, given that the store of the penultimate block now follows it, and that one carries the correct values for those elements already. While at it, simplify the overlapping loads as well, by calculating the address of the final overlapping load upfront, and switching to this address for every load that would otherwise extend past the end of the source buffer. There is no impact on performance, but the resulting code is substantially smaller and easier to follow. Cc: Eric Biggers <ebiggers@google.com> Cc: "Jason A . Donenfeld" <Jason@zx2c4.com> Signed-off-by:
Ard Biesheuvel <ardb@kernel.org> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add support for the QAT gen4 devices in the firmware loader. Signed-off-by:
Jack Xu <jack.xu@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add support for broadcasting mode in firmware loader to enable the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add support for shared ustore mode support. This is required by the next generation of QAT devices to share the same fw image across engines. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Introduce new API, qat_uclo_set_cfg_ae_mask(), to allow the load of the firmware image to a subset of Acceleration Engines (AEs). This is required by the next generation of QAT devices to be able to load different firmware images to the device. Signed-off-by:
Jack Xu <jack.xu@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add firmware control unit (FCU) CSRs to chip info so the firmware authentication code is common between all devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add support for CSS3K, which uses RSA3K as image signature algorithm, to support the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Use ae_mask to decide which Accelerator Engine (AE) to target in AE related operations, instead of a sequential loop, to skip AEs that are fused out. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add null pointer check when freeing the memory for firmware. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add misc control CSR to chip info since the CSR offset will be different in the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add the wake up event to chip info since this value will be different in the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add global clock enable CSR to the chip info since the CSR offset will be different in the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add reset CSR offset and mask to chip info since they are different in new QAT devices. This also simplifies the reset/clrReset functions by using the reset mask. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add the local memory size to the chip info since the size of this memory will be different in the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Add support for local memory lm2 and lm3 which is introduced in the next generation of QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Introduce the next neighbor (NN) capability in chip_info as NN registers are not supported in certain SKUs of QAT. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Modify condition in qat_uclo_wr_mimage() to use a capability of the device (sram_visible), rather than the device ID, so the check is not specific to devices of the same type. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Introduce the chip info structure which contains device specific information. The initialization path has been split between common and hardware specific in order to facilitate the introduction of the next generation hardware. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Replace long expressions with local variables in the functions qat_uclo_wr_uimage_page(), qat_uclo_init_globals() and qat_uclo_init_umem_seg() to improve readability. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Refactor qat_uclo_set_ae_mode() by moving the logic that sets the AE modes to a separate function, qat_hal_set_modes(). Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Move the definition of ICP_QAT_AE_OFFSET, ICP_QAT_CAP_OFFSET, LOCAL_TO_XFER_REG_OFFSET and ICP_QAT_EP_OFFSET from qat_hal.c to icp_qat_hal.h to avoid the definition of generation specific constants in qat_hal.c. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Include the offset of GLOBAL_CSR directly into the enum hal_global_csr and remove the macros SET_GLB_CSR/GET_GLB_CSR to simplify the global CSR access. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Change the API and the behaviour of the qat_hal_start() function. With this change, the function starts under the hood all acceleration engines (AEs) and there is no longer need to call it for each engine. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Change micro word data mask since the Acceleration Engine (AE) instruction codes have been changed in the new generation QAT devices. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Change type for ctx_mask from unsigned char to unsigned long to avoid type casting. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Improve the way micro instructions (FW code) are uploaded to Accelerator Engines (AEs). If code starts at PC zero (absolute addressing), read uwords with no relative address. Otherwise, use relative addressing to the page region. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Rename the function qat_uclo_del_uof_obj() in qat_uclo_del_obj() since it frees the memory allocated for all firmware objects. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Introduce additional parenthesis to resolve a warninga reported by checkpatch. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Remove unnecessary parenthesis across the firmware loader. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Jack Xu authored
Change message in error path of qat_uclo_check_image_compat() to report an incompatible firmware image that contains a neighbor register table. Signed-off-by:
Jack Xu <jack.xu@intel.com> Co-developed-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-