- 30 Apr, 2009 3 commits
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Ingo Molnar authored
Turn on scaling display by default - this is less confusing. Signed-off-by:Ingo Molnar <mingo@elte.hu>
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Ingo Molnar authored
Build it explicitly until it's a proper builtin command. Signed-off-by: -
Paul Mackerras authored
This adds my name to the list of copyright holders on the core perf_counter.c, since I have contributed a significant amount of the code in there. Signed-off-by:
Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Robert Richter <robert.richter@amd.com> LKML-Reference: <18936.59200.888049.746658@cargo.ozlabs.ibm.com> Signed-off-by:
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- 29 Apr, 2009 35 commits
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Robert Richter authored
Standardize on explicitly mentioning '_mask' in fields that are not plain flags but masks. This avoids typos like: if (cpuc->used) (which could easily slip through review unnoticed), while if a typo looks like this: if (cpuc->used_mask) it might get noticed during review. [ Impact: cleanup ] Signed-off-by:Robert Richter <robert.richter@amd.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> LKML-Reference: <1241016956-24648-1-git-send-email-robert.richter@amd.com> Signed-off-by:
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Paul Mackerras authored
POWER5+ and POWER6 have two hardware counters with limited functionality: PMC5 counts instructions completed in run state and PMC6 counts cycles in run state. (Run state is the state when a hardware RUN bit is 1; the idle task clears RUN while waiting for work to do and sets it when there is work to do.) These counters can't be written to by the kernel, can't generate interrupts, and don't obey the freeze conditions. That means we can only use them for per-task counters (where we know we'll always be in run state; we can't put a per-task counter on an idle task), and only if we don't want interrupts and we do want to count in all processor modes. Obviously some counters can't go on a limited hardware counter, but there are also situations where we can only put a counter on a limited hardware counter - if there are already counters on that exclude some processor modes and we want to put on a per-task cycle or instruction counter that doesn't exclude any processor mode, it could go on if it can use a limited hardware counter. To keep track of these constraints, this adds a flags argument to the processor-specific get_alternatives() functions, with three bits defined: one to say that we can accept alternative event codes that go on limited counters, one to say we only want alternatives on limited counters, and one to say that this is a per-task counter and therefore events that are gated by run state are equivalent to those that aren't (e.g. a "cycles" event is equivalent to a "cycles in run state" event). These flags are computed for each counter and stored in the counter->hw.counter_base field (slightly wonky name for what it does, but it was an existing unused field). Since the limited counters don't freeze when we freeze the other counters, we need some special handling to avoid getting skew between things counted on the limited counters and those counted on normal counters. To minimize this skew, if we are using any limited counters, we read PMC5 and PMC6 immediately after setting and clearing the freeze bit. This is done in a single asm in the new write_mmcr0() function. The code here is specific to PMC5 and PMC6 being the limited hardware counters. Being more general (e.g. having a bitmap of limited hardware counter numbers) would have meant more complex code to read the limited counters when freezing and unfreezing the normal counters, with conditional branches, which would have increased the skew. Since it isn't necessary for the code to be more general at this stage, it isn't. This also extends the back-ends for POWER5+ and POWER6 to be able to handle up to 6 counters rather than the 4 they previously handled. Signed-off-by:
Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Robert Richter <robert.richter@amd.com> LKML-Reference: <18936.19035.163066.892208@cargo.ozlabs.ibm.com> Signed-off-by:
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Ingo Molnar authored
Acked-by:
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Robert Richter authored
The documentation about the perf-top build was outdated after perfstat has been implemented. This updates it. [ Impact: update documentation ] Signed-off-by:
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Robert Richter authored
The mask argument is unused and thus can be removed. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
The function fixed_mode_idx() is used generically. Now it checks the num_counters_fixed value instead of the vendor to decide if fixed counters are present. [ Impact: generalize code ] Signed-off-by:
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Robert Richter authored
In x86 pmus the allowed counter period to programm differs. This introduces a max_period value and allows the generic implementation for all models to check the max period. [ Impact: generalize code ] Signed-off-by:
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Robert Richter authored
To check on AMD cpus if a counter overflows, the upper bit of the raw counter value must be checked. This value is already internally available in x86_perf_counter_update(). Now, the value is returned so that it can be used directly to check for overflows. [ Impact: micro-optimization ] Signed-off-by:
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Robert Richter authored
This patch implements the interrupt handler for AMD performance counters. In difference to the Intel pmu, there is no single status register and also there are no fixed counters. This makes the handler very different and it is useful to make the handler vendor specific. To check if a counter is overflowed the upper bit of the counter is checked. Only counters where the active bit is set are checked. With this patch throttling is enabled for AMD performance counters. This patch also reenables Linux performance counters on AMD cpus. [ Impact: re-enable perfcounters on AMD CPUs ] Signed-off-by:
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Robert Richter authored
Some functions are only called if the pmu was proper initialized. That initalization checks can be removed. The way to check initialization changed too. Now, the pointer to the interrupt handler is checked. If it exists the pmu is initialized. This also removes a static variable and uses struct x86_pmu as only data source for the check. [ Impact: simplify code ] Signed-off-by:
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Robert Richter authored
As for the enable function, this patch reworks the disable functions and introduces x86_pmu_disable_counter(). The internal function i/f in struct x86_pmu changed too. [ Impact: refactor and generalize code ] Signed-off-by:
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Robert Richter authored
There is vendor specific code in generic x86 code, and there is vendor specific code that could be generic. This patch introduces x86_pmu_enable_counter() for x86 generic code. Fixed counter code for Intel is moved to Intel only functions. In the end, checks and calls via function pointers were reduced to the necessary. Also, the internal function i/f changed. [ Impact: refactor and generalize code ] Signed-off-by:
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Robert Richter authored
The type of counter index is sometimes implemented as unsigned int. This patch changes this to have a consistent usage of int. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
cpuc->active will now be used to indicate an enabled counter which implies also valid pointers of cpuc->counters[]. In contrast, cpuc->used only locks the counter, but it can be still uninitialized. [ Impact: refactor and generalize code ] Signed-off-by:
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Robert Richter authored
This is to have a consistent naming scheme with cpuc->used. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
[ Impact: micro-optimization ] Signed-off-by:
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Robert Richter authored
This makes the use of the version variable generic. Also, some debug messages have been generalized. [ Impact: refactor and generalize code ] Signed-off-by:
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Robert Richter authored
[ Impact: refactor and generalize code ] Signed-off-by:
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Robert Richter authored
Instead of using a pointer to reference to the x86 pmu we now have one single data structure that is initialized at the beginning. This saves the pointer access when using this memory. [ Impact: micro-optimization ] Signed-off-by:
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Robert Richter authored
This patch adds an error handler and changes initialization of struct x86_pmu. No functional changes. Needed for follow-on patches. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
[ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
[ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
This function is Intel only and not necessary for AMD cpus. [ Impact: simplify code ] Signed-off-by:
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Robert Richter authored
This function is Intel only and not necessary for AMD cpus. [ Impact: simplify code ] Signed-off-by:
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Robert Richter authored
This separates the perfcounter interrupt handler for AMD and Intel cpus. The AMD interrupt handler implementation is a follow-on patch. [ Impact: refactor and clean up code ] Signed-off-by:
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Robert Richter authored
This patch renames struct pmc_x86_ops into struct x86_pmu. It introduces a structure to describe an x86 model specific pmu (performance monitoring unit). It may contain ops and data. The new name of the structure fits better, is shorter, and thus better to handle. Where it was appropriate, names of function and variable have been changed too. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
This patch renames struct hw_perf_counter_ops into struct pmu. It introduces a structure to describe a cpu specific pmu (performance monitoring unit). It may contain ops and data. The new name of the structure fits better, is shorter, and thus better to handle. Where it was appropriate, names of function and variable have been changed too. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
Per-cpu variables needn't to be protected with cpu barriers (smp_wmb()). Protection is only needed for preemption on the same cpu (rescheduling or the nmi handler). This can be done using a compiler barrier only. [ Impact: micro-optimization ] Signed-off-by:
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Robert Richter authored
MSR reads and writes are expensive. This patch adds checks to avoid its usage where possible. [ Impact: micro-optimization on AMD CPUs ] Signed-off-by:
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Robert Richter authored
This quits hw counter initialization immediately if no cpu is detected. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
This is only needed for CONFIG_PERF_COUNTERS enabled. [ Impact: cleanup ] Signed-off-by:
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Robert Richter authored
X86_FEATURE_ARCH_PERFMON is an Intel hardware feature that does not work on AMD CPUs. The flag is now only used in Intel specific code (especially initialization). [ Impact: refactor code ] Signed-off-by:
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Ingo Molnar authored
Merge reason: This brach was on -rc1, refresh it to almost-rc4 to pick up the latest upstream fixes. Signed-off-by: -
git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intelLinus Torvalds authored
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: fix up error path leak in i915_cmdbuffer drm/i915: fix unpaired i915 device mutex on entervt failure. drm/i915: add support for G41 chipset drm/i915: Enable ASLE if present drm/i915: Unregister ACPI video driver when exiting drm/i915: Register ACPI video even when not modesetting drm/i915: fix transition to I915_TILING_NONE drm/i915: Don't let an oops get triggered from irq_emit without dma init. drm/i915: allow tiled front buffers on 965+
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git://git.kernel.org/pub/scm/linux/kernel/git/roland/infinibandLinus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: (21 commits) RDMA/nes: Update iw_nes version RDMA/nes: Fix error path in nes_accept() RDMA/nes: Fix hang issues for large cluster dynamic connections RDMA/nes: Increase rexmit timeout interval RDMA/nes: Check for sequence number wrap-around RDMA/nes: Do not set apbvt entry for loopback RDMA/nes: Fix unused variable compile warning when INFINIBAND_NES_DEBUG=n RDMA/nes: Fix fw_ver in /sys RDMA/nes: Set trace length to 1 inch for SFP_D RDMA/nes: Enable repause timer for port 1 RDMA/nes: Correct CDR loop filter setting for port 1 RDMA/nes: Modify thermo mitigation to flip SerDes1 ref clk to internal RDMA/nes: Fix resource issues in nes_create_cq() and nes_destroy_cq() RDMA/nes: Remove root_256()'s unused pbl_count_256 parameter mlx4_core: Fix memory leak in mlx4_enable_msi_x() IB/mthca: Fix timeout for INIT_HCA and a few other commands RDMA/cxgb3: Don't zero QP attrs when moving to IDLE RDMA/nes: Fix bugs in nes_reg_phys_mr() RDMA/nes: Fix compiler warning at nes_verbs.c:1955 IPoIB: Disable NAPI while CQ is being drained ...
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- 28 Apr, 2009 2 commits
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Geert Uytterhoeven authored
Fix this: arch/m68k/kernel/sun3-head.S: Assembler messages: arch/m68k/kernel/sun3-head.S:32: Error: Unknown operator -- statement `__head' ignored Introduced by commit 6f335cab ("m68k: convert to use __HEAD and HEAD_TEXT macros."), which started using __HEAD without adding the appropriate include. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.dk/linux-2.6-blockLinus Torvalds authored
* 'for-linus' of git://git.kernel.dk/linux-2.6-block: bio: fix memcpy corruption in bio_copy_user_iov() hd: fix locking mg_disk: fix CONFIG_LBD=y warning mg_disk: fix locking
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