- 27 May, 2022 9 commits
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Ville Syrjälä authored
During the eDP probe we may not yet know the panel_type used to index the VBT panel tables. So the initial eDP probe will have to be done without that, and thus we won't yet have the PPS delays from the VBT. Once the VBT has been fully parse we should reinit the PPS delays to make sure it's fully accounted for. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-9-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Split the PPS init to something we do at the start of the eDP probe and a second part we do at the end. Signed-off-by:
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Ville Syrjälä authored
In order to do the panel VBT parsing after the EDID read (needed to determine panel_type from PNPID) we need to stash away the original BIOS programmed PPS delays so that we can consult them again when we reinit the PPS delays after the VBT parsing has been done. Signed-off-by:
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Ville Syrjälä authored
Skip QUIRK_INCREASE_T12_DELAY and the t11_t12 adjustment of the VBT PPS delays if we've not yet initialized them. Will be important later when the PPS delay init can happen before VBT parsing. Signed-off-by:
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Ville Syrjälä authored
Add a small helper that determines if the PPS delays have been initialized or not. Signed-off-by:
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Ville Syrjälä authored
Split each of the hw/vbt/spec PPS delay initialization into separate functions to make the whole thing less cluttered. Signed-off-by:
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Ville Syrjälä authored
We have the same "override eDP VBT bpp with the current bpp" code duplciated in two places. Extract it to a helper function. TODO: Having this in .get_config() is pretty ugly. Should probably try to move it somewhere else (setup_hw_state()/etc.)... Signed-off-by:
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Ville Syrjälä authored
Pass intel_connector instead of drm_connector to intel_vrr_is_capable(). Will result in less ugly casts. Signed-off-by:
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Balasubramani Vivekanandan authored
New updates to HDMI combo PHY voltage swing tables. Actually with this update (bspec updated on 08/17/2021), the values are reverted back to be same as icelake for HDMI combo PHY. Bspec: 49291 Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220526064935.969225-1-balasubramani.vivekanandan@intel.com
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- 25 May, 2022 1 commit
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Vandita Kulkarni authored
This patch adds a fix to support 297MHz of dot clock by calculating the pll values using synopsis algorithm. This will help to support 4k@30 mode for HDMI monitors on DG2. v2: As per the algorithm, set MPLLB VCO range control bits to 3, in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt) v3: Fix typo. (Ankit) Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
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- 24 May, 2022 1 commit
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Julia Lawall authored
Spelling mistakes (triple letters) in comments. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by:
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- 23 May, 2022 3 commits
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Imre Deak authored
Based on a bspec update the DMC firmware's flip queue handling events need to be disabled before enabling DC5/6. i915 doesn't use the flip queue feature atm, so disable it already after loading the firmware. This removes some overhead of the event handler which runs at a 1 kHz frequency. Bspec: 49193, 72486, 72487 v2: - Fix the DMC pipe A register offsets for GEN12. - Disable the events on DG2 only on pipe A..D . v3: (Lucas) - Add TODO: to clarify the disabling sequence on all D13+ - s/intel_dmc_has_fw_payload/has_dmc_id_fw/ - s/simple_flipq/flipq/ - s/_GEN12,_GEN13/TGL_,ADLP_/ - s/MAINDMC/DMC/ v4: - Only disable flip queues on TGL/DG2, as on other platforms the corresponding event handlers don't exist. Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> # v1 Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220521130808.637449-1-imre.deak@intel.com
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Ville Syrjälä authored
Give block_size()/block_offset() a "raw_" prefix since they both operate on the "raw" (as in not duplicated) BDB block contents. What actually spurred this was a conflict between intel_bios.c block_size() vs. block_size() from blkdev.h. That only happened to me on a custom tree where we somehow manage to include blkdev.h into intel_bios.c. But I think the rename makes sense anyway to clarify the purpose of these functions. Signed-off-by:
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Jani Nikula authored
The VBT send packet port selection was never updated for ICL+ where the 2nd link is on port B instead of port C as in VLV+ DSI. First, single link DSI needs to use the configured port instead of relying on the VBT sequence block port. Remove the hard-coded port C check here and make it generic. For reference, see commit f915084e ("drm/i915: Changes related to the sequence port no for") for the original VLV specific fix. Second, the sequence block port number is either 0 or 1, where 1 indicates the 2nd link. Remove the hard-coded port C here for 2nd link. (This could be a "find second set bit" on DSI ports, but just check the two possible options.) Third, sanity check the result with a warning to avoid a NULL pointer dereference. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5984 Cc: stable@vger.kernel.org # v4.19+ Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by:
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- 20 May, 2022 3 commits
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Dale B Stimson authored
Some dGfx pcode commands take additional sub-commands and parameters. Add a couple of helpers to help formatting these commands to improve code readability. v2: Fixed commit author (Rodrigo) v3: Function rename and convert to new uncore interface for pcode functions Remove unnecessary #define's (Andi) v4: Another function rename Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-3-tvrtko.ursulin@linux.intel.com
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Ashutosh Dixit authored
Each gt contains an independent instance of pcode. Extend pcode functions to interface with pcode on different gt's. To avoid creating dependency of display functionality on intel_gt, pcode function interfaces are exposed in terms of uncore rather than intel_gt. Callers have been converted to pass in the appropritate (i915 or intel_gt) uncore to the pcode functions. v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo) v3: Retain previous function names to eliminate needless #defines (Rodrigo) v4: Move out i915_pcode_init() to a separate patch (Tvrtko) Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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Ashutosh Dixit authored
Media ratio mode (the ability for media IP to work at a different frequency from the GT) is available for a subset of dGfx platforms supporting GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to identify these platforms and set it for XEHPSDV and DG2/ATS-M. Signed-off-by:
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- 19 May, 2022 1 commit
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Jani Nikula authored
Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to -fsanitize=shift. References: https://lore.kernel.org/r/20220405151517.29753-12-bp@alien8.deReported-by:
Borislav Petkov <bp@suse.de> Reported-by:
Ruiqi GONG <gongruiqi1@huawei.com> Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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- 16 May, 2022 3 commits
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Jouni Högander authored
Current update area calculation is not handling situation where e.g. cursor plane is fully or partially outside pipe area. Fix this by checking damage area against pipe_src area using drm_rect_intersect. v2: Set x1 and x2 in damaged_area initialization v3: Move drm_rect_intersect into clip_area_update v4: draw_area -> pipe_src Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440 Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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Jouni Högander authored
Currently we have some corner cases where area calculation fails. For these sel fetch area calculation ends up having update area as y1 = 0, y2 = 4. Instead of these values safer option is full update. One of such for example is big fb with offset. We don't have usable offset in psr2_sel_fetch_update. Currently it's open what is the proper way to fix this corner case. Use full update for now. v2: Commit message modified v3: Print out debug info once when area calculation fails v4: Use drm_info_once v5: pipeA -> "pipe %c", pipe_name(crtc-pipe) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Anshuman Gupta authored
RPM suspend/resume also supported on gfx platforms which doesn't have kms support and even on platforms without any connected display panel. There is no good reason to log rpm suspend/resume debug message with drm_dbg_kms() therefore changing it to drm_dbg(). Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by:
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- 13 May, 2022 2 commits
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Jani Nikula authored
Need to use pipe_name(pipe) instead of pipe directly. Fixes: 1f31e35f ("drm/i915/audio: unify audio codec enable/disable debug logging") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Anusha Srivatsa authored
Bspec has added some steps that check forDMC MMIO range before programming them v2: Fix for CI v3: move register defines to .h (Anusha) - Check MMIO restrictions per pipe - Add MMIO restricton for v1 dmc header as well (Lucas) v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario. - clean up sanity check logic.(Lucas) - Add MMIO range for RKL as well.(Anusha) v5: Use DISPLAY_VER instead of per platform check (Lucas) BSpec: 49193 Cc: stable@vger.kernel.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
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- 12 May, 2022 1 commit
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Imre Deak authored
Fix the following sparse warnings: drivers/gpu/drm/i915/display/intel_display_power.c:2431:34: warning: mixing different enum types: drivers/gpu/drm/i915/display/intel_display_power.c:2431:34: unsigned int enum intel_display_power_domain drivers/gpu/drm/i915/display/intel_display_power.c:2431:34: int enum port drivers/gpu/drm/i915/display/intel_display_power.c:2442:37: warning: mixing different enum types: drivers/gpu/drm/i915/display/intel_display_power.c:2442:37: unsigned int enum intel_display_power_domain drivers/gpu/drm/i915/display/intel_display_power.c:2442:37: int enum port drivers/gpu/drm/i915/display/intel_display_power.c:2468:43: warning: mixing different enum types: drivers/gpu/drm/i915/display/intel_display_power.c:2468:43: unsigned int enum intel_display_power_domain drivers/gpu/drm/i915/display/intel_display_power.c:2468:43: unsigned int enum aux_ch drivers/gpu/drm/i915/display/intel_display_power.c:2479:35: warning: mixing different enum types: drivers/gpu/drm/i915/display/intel_display_power.c:2479:35: unsigned int enum intel_display_power_domain drivers/gpu/drm/i915/display/intel_display_power.c:2479:35: unsigned int enum aux_ch Fixes: 979e1b32 ("drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform") Reported-by:
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- 11 May, 2022 1 commit
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Anusha Srivatsa authored
Add Support for DC states on Dg2. v2: Add dc9 as the max supported DC states and disable DC5. v3: set max_dc to 0. (Imre) Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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- 09 May, 2022 2 commits
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Jani Nikula authored
Reduce the magic of what's going on in GEM_DEBUG_EXEC() by expanding it inline and being explicit about it. It's as single use case anyway, so the macro feels overkill. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Jani Nikula authored
There are already too many choices here, take away the unused ones. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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- 05 May, 2022 10 commits
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Ville Syrjälä authored
Make sure our choice of downclock mode respects the VBT seameless DRRS min refresh rate limit. v2: s/vrefesh/vrefresh/ (Jani) Reviewed-by:
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Ville Syrjälä authored
Extract the seamless DRRS min refresh rate from the VBT. v2: Do a version check Reviewed-by:
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Ville Syrjälä authored
Make the panel type code a bit more abstract along the lines of the source of the panel type. For the moment we have three classes: OpRegion, VBT, fallback. Well introduce another one shortly. We can now also print out all the different panel types, and indicate which one we ultimately selected. Could help with debugging. v2: Add .get_panel_type() vfunc (Jani) Reviewed-by:
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Ville Syrjälä authored
Pull the code to determine the panel type into its own set of sane functions. v2: rebase Reviewed-by:
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Ville Syrjälä authored
Just assume panel_type==0 always if the VBT gives us bogus data. We actually already do this everywhere else except in parse_panel_options() since we just leave i915->vbt.panel_type zeroed. This also seems to be what Windows does. Reviewed-by:
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Ville Syrjälä authored
Document the fact that struct lvds_lfp_data_entry can't be used directly and instead must be accessed via the data table pointers. Also remove the bogus comment implying that there might be a variable number of panel entries in the table. There are always exactly 16. Reviewed-by:
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Ville Syrjälä authored
We need to start parsing stuff from the tail end of the LFP data block. This is made awkward by the fact that the fp_timing table has variable size. So we must use a bit more finesse to get the tail end, and to make sure we allocate enough memory for it to make sure our struct representation fits. v2: Rebase due to the preallocation of BDB blocks v3: Rebase due to min_size WARN relocation v4: Document BDB_LVDS_LFP_DATA vs. BDB_LVDS_LFP_DATA_PTRS order (Jani) Reviewed-by:
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Ville Syrjälä authored
Modern VBTs no longer contain the LFP data table pointers block (41). We are expecting to have one in order to be able to parse the LFP data block (42), so let's make one up. Since the fp_timing table has variable size we must somehow determine its size. Rather than just hardcode it we look for the terminator bytes (0xffff) to figure out where each table entry starts. dvo_timing, panel_pnp_id, and panel_name are expected to have fixed size. This has been observed on various machines, eg. TGL with BDB version 240, CML with BDB version 231, etc. The most recent VBT I've observed that still had block 41 had BDB version 228. So presumably the cutoff (if an exact cutoff even exists) is somewhere around BDB version 229-231. v2: kfree the thing we allocated, not the thing+3 bytes v3: Do the debugprint only if we found the LFP data block v4: Fix t0 null check (Jani) Reviewed-by:
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Ville Syrjälä authored
Reorder things so that we can parse the entier LFP data block in one go. For now we just stick to parsing the DTD from it. Also fix the misleading comment about block 42 being deprecated. Only the DTD part is deprecated, the rest is still very much needed. v2: Move the version check+comment into parse_generic_dtd() (Jani) Reviewed-by:
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Ville Syrjälä authored
Initialize on-stack modes with drm_mode_init() to guarantee no stack garbage in the list head, or that we aren't copying over another mode's list head. Based on the following cocci script, with manual fixups: @decl@ identifier M; expression E; @@ - struct drm_display_mode M = E; + struct drm_display_mode M; @@ identifier decl.M; expression decl.E; statement S, S1; @@ struct drm_display_mode M; ... when != S + drm_mode_init(&M, &E); + S1 @@ expression decl.E; @@ - &*E + E Signed-off-by:
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- 04 May, 2022 1 commit
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Jani Nikula authored
Make sure each DDI platform has sane ->get_buf_trans initialized. Suggested-by:
Arun R Murthy <arun.r.murthy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503082134.4128355-1-jani.nikula@intel.com
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- 02 May, 2022 1 commit
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Jani Nikula authored
Using compound literals for initialization can be tricky. Lacking a const qualifier, they won't end up in rodata, which is probably not expected or intended. Add const to move a whopping 136 initializers to rodata. Compare: $ objdump --syms drivers/gpu/drm/i915/display/intel_display_power_map.o | grep "\.rodata.*__compound_literal" $ objdump --syms drivers/gpu/drm/i915/display/intel_display_power_map.o | grep "\.data.*__compound_literal" Before and after the change. Fixes: c32ffce4 ("drm/i915: Convert the power well descriptor domain mask to an array of domains") Fixes: 4a845ff0 ("drm/i915: Simplify power well definitions by adding power well instances") Cc: Imre Deak <imre.deak@intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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- 29 Apr, 2022 1 commit
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https://github.com/intel/gvt-linuxJani Nikula authored
gvt-next-2022-04-29 Introduce fixes from previous pull. - Fix a compiling warning of non-static funtion only having one caller. - Fix a potential NULL pointer reference in the code re-factor. - Fix a compiling error when CONFIG_DRM_I915_DEBUG_RUNTIME_PM=n Signed-off-by:
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