1. 03 Sep, 2015 12 commits
    • Markos Chandras's avatar
      MIPS: Kconfig: Drop the EXPERIMENTAL tag from MIPS R6 · 674d10e2
      Markos Chandras authored
      The MIPS R6 ISA support has been part of mainline since v4.0
      and it should be in a good shape nowadays so it is not an
      experimental feature anymore.
      Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/10731/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      674d10e2
    • Ralf Baechle's avatar
      MIPS: Treat CP1 control registers as unsigned ints. · c46a2f01
      Ralf Baechle authored
      These are bitfields and treating them as signed values doesn't make
      any sense.
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Reported-by: default avatarChris Packham <judge.packham@gmail.com>
      c46a2f01
    • Chris Packham's avatar
      MIPS: Use unsigned int when reading CP0 registers · 82eb8f73
      Chris Packham authored
      Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
      use "unsigned int res;" instead of "int res;". There is little reason to
      treat these register values as signed. They are either counters (which
      by definition are unsigned) or are made up of various bit fields to be
      interpreted as per the CPU datasheet.
      
      This has come up via u-boot[1] which sync's asm/mipsregs.h with the
      kernel. In u-boots case the value read from read_c0_count() is assigned
      to an unsigned long [2] which triggers a sign extension and causes a
      bug.
      
      U-boot should probably be more explicit about the types used for the
      timer_read_counter() API but that aside is there any reason to treat
      these values as signed integers? A quick grep around the arch/mips makes
      me thing that there may be some bugs lurking when read_c0_count() starts
      to yield a negative value but I haven't really explored any of them.
      
      [1] - http://lists.denx.de/pipermail/u-boot/2015-July/219086.html
      [2] - http://git.denx.de/?p=u-boot.git;a=blob;f=arch/mips/cpu/time.c#l11Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      Cc: Chris Packham <judge.packham@gmail.com>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10718/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      82eb8f73
    • Paul Burton's avatar
      MIPS: malta: Use generic platform_maar_init · 570e5d26
      Paul Burton authored
      The default implementation of platform_maar_init is sufficient for Malta
      boards where we want to allow speculation in the regions of memory
      corresponding to DDR & disallow it elsewhere. Drop the custom
      implementation such that the default is used, reducing the duplication
      of information provided by the Malta platform code.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10677/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      570e5d26
    • Paul Burton's avatar
      MIPS: mm: default platform_maar_init using bootmem data · cbd95a89
      Paul Burton authored
      Introduce a default weak implementation of platform_maar_init which
      makes use of the data that platforms already provide to the bootmem
      allocator. This should hopefully cover the most common configurations,
      reduce the duplication of information provided by platforms & leaves
      platforms with the option of providing a custom implementation if
      required.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Patchwork: https://patchwork.linux-mips.org/patch/10676/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      cbd95a89
    • Leonid Yegoshin's avatar
      MIPS: MSA unaligned memory access support · e4aa1f15
      Leonid Yegoshin authored
      The MSA architecture specification allows for hardware to not implement
      unaligned vector memory accesses in some or all cases. A typical example
      of this is the I6400 core which does not implement unaligned vector
      memory access when the memory crosses a page boundary. The architecture
      also requires that such memory accesses complete successfully as far as
      userland is concerned, so the kernel is required to emulate them.
      
      This patch implements support for emulating unaligned MSA ld & st
      instructions by copying between the user memory & the tasks FP context
      in struct thread_struct, updating hardware registers from there as
      appropriate in order to avoid saving & restoring the entire vector
      context for each unaligned memory access.
      
      Tested both using an I6400 CPU and with a QEMU build hacked to produce
      AdEL exceptions for unaligned vector memory accesses.
      
      [paul.burton@imgtec.com:
        - Remove #ifdef's
        - Move msa_op into enum major_op rather than #define
        - Replace msa_{to,from}_wd with {read,write}_msa_wr_{b,h,w,l} and the
          format-agnostic wrappers, removing the custom endian mangling for
          big endian systems.
        - Restructure the msa_op case in emulate_load_store_insn to share
          more code between the load & store cases.
        - Avoid the need for a temporary union fpureg on the stack by simply
          reusing the already suitably aligned context in struct
          thread_struct.
        - Use sizeof(*fpr) rather than hardcoding 16 as the size for user
          memory checks & copies.
        - Stop recalculating the address of the unaligned vector memory access
          and rely upon the value read from BadVAddr as we do for other
          unaligned memory access instructions.
        - Drop the now unused val8 & val16 fields in union fpureg.
        - Rewrite commit message.
        - General formatting cleanups.]
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-kernel@vger.kernel.org
      Cc: Jie Chen <chenj@lemote.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10573/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e4aa1f15
    • Paul Burton's avatar
      MIPS: Introduce accessors for MSA vector registers · 6b35e114
      Paul Burton authored
      Introduce accessor functions allowing the kernel to access arbitrary
      vector registers using an arbitrary data format. The accessors are
      implemented in assembly, using macros to avoid massive duplication, in
      order to make use of the existing support for MSA with & without
      toolchain support. The accessors will be used in a later patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: Manuel Lauss <manuel.lauss@gmail.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10572/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6b35e114
    • Leonid Yegoshin's avatar
      MIPS: Declare MSA MI10 instruction formats · 6701ca2d
      Leonid Yegoshin authored
      Declare a struct describing the MSA MI10 instruction format used for ld &
      st instructions, for use by subsequent patches.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10571/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6701ca2d
    • Bjorn Helgaas's avatar
      MIPS: Remove "__weak" definition from arch-specific linkage.h · b620c972
      Bjorn Helgaas authored
      "__weak" is defined in include/linux/compiler-gcc.h.  We shouldn't need an
      arch-specific definition.
      
      Remove the "__weak" definition from arch/mips/include/asm/linkage.h.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/10689/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b620c972
    • Bjorn Helgaas's avatar
      MIPS: Remove "weak" from mips_cdmm_phys_base() declaration · e1d97497
      Bjorn Helgaas authored
      Weak header file declarations are error-prone because they make every
      definition weak, and the linker chooses one based on link order (see
      10629d71 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node
      decl")).
      
      mips_cdmm_phys_base() is defined only in arch/mips/mti-malta/malta-memory.c
      so there's no problem with multiple definitions.  But it works better to
      have a weak default implementation and allow a strong function to override
      it.  Then we don't have to test whether a definition is present, and if
      there are ever multiple strong definitions, we get a link error instead of
      calling a random definition.
      
      Add a weak mips_cdmm_phys_base() definition and remove the weak annotation
      from the declaration in arch/mips/include/asm/cdmm.h.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/10688/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e1d97497
    • Bjorn Helgaas's avatar
      MIPS: Remove "weak" from get_c0_fdc_int() declaration · 770847ba
      Bjorn Helgaas authored
      Weak header file declarations are error-prone because they make every
      definition weak, and the linker chooses one based on link order (see
      10629d71 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node
      decl")).
      
      The most elegant solution is to have a weak default implementation and
      allow a strong function to override it.  Then we don't have to test
      whether a definition is present, and if there are ever multiple strong
      definitions, we get a link error instead of calling a random definition.
      
      Add a weak get_c0_fdc_int() definition with the default code and remove the
      weak annotation from the declaration.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/10687/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      770847ba
    • Bjorn Helgaas's avatar
      MIPS: Remove "weak" from get_c0_compare_int() declaration · ec0b9d35
      Bjorn Helgaas authored
      Weak header file declarations are error-prone because they make every
      definition weak, and the linker chooses one based on link order (see
      10629d71 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node
      decl")).
      
      get_c0_compare_int() is defined in several files.  Each definition is weak,
      so I assume Kconfig prevents two or more from being included.  The caller
      contains default code used when get_c0_compare_int() isn't defined at all.
      
      Add a weak get_c0_compare_int() definition with the default code and remove
      the weak annotation from the declaration.
      
      Then the platform implementations will be strong and will override the weak
      default.  If multiple platforms are ever configured in, we'll get a link
      error instead of calling a random platform's implementation.
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/10686/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ec0b9d35
  2. 26 Aug, 2015 28 commits