- 02 Nov, 2020 6 commits
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Isabel Zhang authored
[Why] On APU should be always using prefetch mode 0. Currently, sometimes prefetch mode 1 is being used causing system to hard hang due to minTTUVBlank being too low. [How] Any ASIC running DCN21 will by default allow self refresh and mclk switch. This sets both min and max prefetch mode to 0 by default. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yongqiang Sun authored
[Why & How] 1. only need to check first ODM pipe. 2. Only need to check eDP which is on. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Jacky Liao authored
[Why] The MPC memory blocks in DCN3 should be powered down completely when they are not in use. This will reduce power consumption. [How] This commits changes behaviour for dcn3 and does the following: 1. Write to MPC_RMU<X>_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to automatically shut down memory when not in use 2. mpc3_power_on_shaper_3dlut and mpc3_power_on_ogam_lut are called to disable force power on when configuration finishes 3. Added a debug option to allow this behaviour to be turned off Signed-off-by:
Jacky Liao <ziyu.liao@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Tao.Huang authored
[Why] The C standard does not specify whether an enum is signed or unsigned. In the function prototype, one of the argument is defined as an enum but its declaration was unit32_t. Fix this by changing the function argument to enum in the declaration. Signed-off-by:
Tao.Huang <Tao.Huang@amd.com> Signed-off-by:
Florin Iucha <florin.iucha@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Arnd Bergmann authored
gcc -Wextra warns about a function taking an enum argument being called with a bool: drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c: In function 'apply_degamma_for_user_regamma': drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1617:29: warning: implicit conversion from 'enum <anonymous>' to 'enum dc_transfer_func_predefined' [-Wenum-conversion] 1617 | build_coefficients(&coeff, true); It appears that a patch was added using the old calling conventions after the type was changed, and the value should actually be 0 (TRANSFER_FUNCTION_SRGB) here instead of 1 (true). Fixes: 55a01d40 ("drm/amd/display: Add user_regamma to color module") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Veerabadhran Gopalakrishnan authored
Concurrent operation of VCN and JPEG decoder in DPG mode is causing ring timeout due to power state. Signed-off-by:
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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- 30 Oct, 2020 34 commits
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Bas Nieuwenhuizen authored
We're unconditionally using modifiers internally for GFX9+ now. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
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Bas Nieuwenhuizen authored
This expose modifier support on GFX9+. Only modifiers that can be rendered on the current GPU are added. This is to reduce the number of modifiers exposed. The HW could expose more, but the best mechanism to decide what to expose without an explosion in modifiers is still to be decided, and in the meantime this should not regress things from pre-modifiers and does not risk regressions as we make up our mind in the future. v2: - Added comment that D on Raven is only valid for 64bpp and will be filtered based on format later. - Removed D tiling modes that weren't useful for 64bpp on GFX10+. v4: Add AMDGPU_FAMILY_VGH case. Signed-off-by: -
Bas Nieuwenhuizen authored
For DCC we will use 2/3 planes to avoid X rendering to the frontbuffer with DCC compressed images. To make this work with the core KMS validation we need to add extra formats with the extra planes. However, due to flexibility we set bpp = 0 for the extra planes and do the validation ourselves. Signed-off-by:
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Bas Nieuwenhuizen authored
This sets the DC tiling options from the modifier, if modifiers are used for the FB. This patch by itself does not expose the support yet though. There is not much validation yet to limit the scope of this patch, but the current validation is at the same level as the BO metadata path. v2: Add modifier check to should_reset_plane. Signed-off-by:
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Bas Nieuwenhuizen authored
Prepare for inserting modifiers based configuration, while sharing a bunch of DCC validation & initializing the device-based configuration. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Bas Nieuwenhuizen authored
This way the modifier path gets exercised all the time, improving testing. Furthermore, for modifiers this is required as getfb2 will always return the modifier if the driver sets allow_fb_modifiers. This only triggers once allow_fb_modifiers is set. Signed-off-by:
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Bas Nieuwenhuizen authored
This moves the tiling_flags to the framebuffer creation. This way the time of the "tiling" decision is the same as it would be with modifiers. Signed-off-by:
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Bas Nieuwenhuizen authored
This adds modifiers for GFX9+ AMD GPUs. As the modifiers need a lot of parameters I split things out in getters and setters. - Advantage: simplifies the code a lot - Disadvantage: Makes it harder to check that you're setting all the required fields. The tiling modes seem to change every generation, but the structure of what each tiling mode is good for stays really similar. As such the core of the modifier is - the tiling mode - a version. Not explicitly a GPU generation, but splitting out a new set of tiling equations. Sometimes one or two tiling modes stay the same and for those we specify a canonical version. Then we have a bunch of parameters on how the compression works. Different HW units have different requirements for these and we actually have some conflicts here. e.g. the render backends need a specific alignment but the display unit only works with unaligned compression surfaces. To work around that we have a DCC_RETILE option where both an aligned and unaligned compression surface are allocated and a writer has to sync the aligned surface to the unaligned surface on handoff. Finally there are some GPU parameters that participate in the tiling equations. These are constant for each GPU on the rendering/texturing side. The display unit is very flexible however and supports all of them :| Some estimates: - Single GPU, render+texture: ~10 modifiers - All possible configs in a gen, display: ~1000 modifiers - Configs of actually existing GPUs in a gen: ~100 modifiers For formats with a single plane everything gets put in a separate DRM plane. However, this doesn't fit for some YUV formats, so if the format has >1 plane, we let the driver pack the surfaces into 1 DRM plane per format plane. This way we avoid X11 rendering onto the frontbuffer with DCC, but still fit into 4 DRM planes. Signed-off-by: -
Bas Nieuwenhuizen authored
With modifiers I'd like to support non-dedicated buffers for images. Signed-off-by:
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Bas Nieuwenhuizen authored
Otherwise the field ends up being used uninitialized when enabling modifiers, failing validation with high likelyhood. v4: Use memset Signed-off-by:
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Bas Nieuwenhuizen authored
Silently accepting it could result in corruption. Signed-off-by:
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Evan Quan authored
Fix the compile warnings below: >> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13: warning: variable 'min' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] >> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13: warning: variable 'max' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] Signed-off-by:
Evan Quan <evan.quan@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
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Evan Quan authored
Fix the warning below: >> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:29: warning: no previous prototype for function 'asic_internal_ss_get_ss_table' [-Wmissing-prototypes] ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) ^ drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:1: note: declare 'static' if the function is not intended to be used outside of this translation unit ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) ^ static 1 warning generated. Signed-off-by: -
Bhaskar Chowdhury authored
Correct spelling in one of the comment. s/defalut/default/p Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by:
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Arnd Bergmann authored
core_link_write_dpcd() returns enum dc_status, not ddc_result: display/dc/core/dc_link_dp.c: In function 'dp_set_panel_mode': display/dc/core/dc_link_dp.c:4237:11: warning: implicit conversion from 'enum dc_status' to 'enum ddc_result' [-Wenum-conversion] Avoid the warning by using the correct enum in the caller. Fixes: 0b226322 ("drm/amd/display: Synchronous DisplayPort Link Training") Signed-off-by:
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Tom Rix authored
A semicolon is not needed after a switch statement. Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Tom Rix authored
A semicolon is not needed after a switch statement. Signed-off-by:
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Colin Ian King authored
A recent change added two uint16_t elements to PPTable_t and reduced the uint32_t array down to 8 elements. This results in the dev_info printing of pptable->SkuReserved[8] accessing a value that is out-of-range on array SkuReserved. The array has been shrunk by 1 element, so remove this extraneous dev_info message. Addresses-Coverity: ("Out-of-bounds read") Fixes: 1dc3c5a9 ("drm/amd/pm: update driver if file for sienna cichlid") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Zou Wei authored
Fix the following coccinelle report: ./drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:1367:3-5: WARNING: possible condition with no effect (if == else) Both branches are the same, so remove the if/else altogether. Fixes: 81875979 ("drm/amd/display: Remove extra pairs of parentheses in dce_calcs.c") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Zou Wei <zou_wei@huawei.com> Signed-off-by:
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Alex Deucher authored
Not needed. Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Alex Deucher authored
It's unused and identical to dal_cmd_tbl_helper_dce112_get_table2. Reviewed-by:
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Alex Deucher authored
No need for a separate config option at this point. Reviewed-by:
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Alex Deucher authored
Leads to improper dpm on older parts. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1353 Fixes: 8d89b96f ("drm/amd/powerplay: optimize the mclk dpm policy settings") Reviewed-by:
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Joe Perches authored
commit e098bc96 ("drm/amd/pm: optimize the power related source code layout") moved the directory, update the F: file pattern to match. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Evan Quan authored
This reverts commit f8781228 ("drm/amdgpu: Fix bug where DPM is not enabled after hibernate and resume"). It was intended to fix Hawaii S4(hibernation) issue but break S3. As ixFEATURE_STATUS is filled with garbage data on resume which can be only cleared by reloading smc firmware(but that will involve many changes). So, we will revert this S4 fix and seek a new way. Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Reviewed-by:
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Evan Quan authored
So that the succeeding resume can be performed based on a clean state. Signed-off-by:
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Evan Quan authored
Which can be used for S4(hibernation) support. Signed-off-by:
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Evan Quan authored
Correct some registers bitmasks and add mmBIOS_SCRATCH_7 reset. Signed-off-by:
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Evan Quan authored
This can address the random SDMA hang after pci config reset seen on Hawaii. Signed-off-by:
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Chengming Gui authored
Use ">= CHIP_SIENNA_CICHLID" to replace per asic check Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Hawking.Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jinzhou.Su authored
Add RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK Signed-off-by:
Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Christian König authored
First of all don't snprintf into a char buffer allocated on the stack with a constant hubname. Then cleanup to exit the function early in case of a ratelimit or SRIOV. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
We need this to pass dp compliance. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Nikola Cornij <nikola.cornij@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Kent Russell authored
Since the unique_id is now obtained in amdgpu in smu_late_init, topology misses getting the value during KFD device initialization. To work around this, we use amdgpu_amdkfd_get_unique_id to get the unique_id at read time. Due to this, we can remove unique_id from the kfd_dev structure, since we only need it in the KFD node properties struct Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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