- 15 Mar, 2022 26 commits
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Stanley.Yang authored
It should notice SMU to update bad channel info when detected uncorrectable error in UMC block Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Stanley.Yang authored
support message SMU update bad channel info to update HBM bad channel info in OOB table Signed-off-by:
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Melissa Wen authored
FPU operations in dcn10 was already moved to dml folder via calcs code. However, dcn1_0_ip and dcn_1_0_soc with FPU componentd remains on dcn10. Following previous changes to isolate FPU, this patch creates dcn10_fpu files to isolate FPU-specific code and moves those structs to it. Signed-off-by:
Melissa Wen <mwen@igalia.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Melissa Wen authored
dml/dcn20_fpu file centralizes all DCN2x functions that require FPU access. Therefore, this patch moves FPU-related code from dcn21 to dcn20_fpu. These include: - dcn21_populate_dml_pipes_from_context() - dcn21_validate_bandwidth_fp() and related: - dcn21_calculate_wm(), - patch_bounding_box(), - calculate_wm_set_for_vlevel() - renaming update_bw_bounding_box() to dcn21_update_bw_bounding_box(), move to dcn20_fpu with related static function construct_low_pstate_lvl() Also, make dcn21_fast_validate_bw() public in dcn21_resource as it is called by dcn21_validate_bandwidth_fp() now in dcn20_fpu. Reuse dcn20_fpu_adjust_dppclk() in dcn21_fast_validate_bw() as it isolates the same FPU operation. Include dchubbub.h as it is required in dcn21_populate_dml_pipes_from_context() Signed-off-by:
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Melissa Wen authored
Move parts of dcn20 code that uses FPU to dml folder. It aims to isolate FPU operations as described by series: drm/amd/display: Introduce FPU directory inside DC https://patchwork.freedesktop.org/series/93042/ This patch moves the following functions from dcn20_resource to dml/dcn20_fpu and calls of public functions in dcn20_resource are wrapped by DC_FP_START/END(): - void dcn20_populate_dml_writeback_from_context - static bool is_dtbclk_required() - static enum dcn_zstate_support_state() - void dcn20_calculate_dlg_params() - static void swizzle_to_dml_params() - int dcn20_populate_dml_pipes_from_context() - void dcn20_calculate_wm() - void dcn20_cap_soc_clocks() - void dcn20_update_bounding_box() - void dcn20_patch_bounding_box() - bool dcn20_validate_bandwidth_fp() This movement also affects dcn21/30/31, as dcn20_calculate_dlg_params() is used by them. For this reason, I included dcn20_fpu headers in dcn20_resource headers to make dcn20_calculate_dlg_params() visible to dcn21/30/31. Three new functions are created to isolate well-delimited FPU operations: - void dcn20_fpu_set_wb_arb_params(): set cli_watermark, pstate_watermark and time_per_pixel from wb_arb_params (struct mcif_arb_params), since those uses FPU operations on double types: WritebackUrgentWatermark, WritebackDRAMClockChangeWatermark, '16.0'. - void dcn20_fpu_set_wm_ranges(): set min_fill_clk_mhz and max_fill_clk_mhz involves FPU calcs on dram_speed_mts (double type); - void dcn20_fpu_adjust_dppclk(): adjust operation on RequiredDPPCLK that is a double. Signed-off-by:
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Leo Li authored
[Why] On LNX, TO_CLK_MGR_INTERNAL() only works to get clk_mgr_internal from a given clk_mgr. In clk_mgr_dcn316 struct, the clk_mgr_internal is already a memeber by the alias 'base' [How] Use &clk_mgr->base instead. Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] The issue only occurs during the GPU reset code path. We first backup the current state prior to commiting 0 streams internally from DM to DC. This state backup contains valid link encoder assignments. DC will clear the link encoder assignments as part of current state (but not the backup, since it was a copied before the commit) and free the extra stream reference it held. DC requires that the link encoder assignments remain cleared/invalid prior to commiting. Since the backup still has valid assignments we call the interface post reset to clear them. This routine also releases the extra reference that the link encoder interface held - resulting in a double free (and eventually a NULL pointer dereference). [How] We'll have to do a full DC commit anyway after GPU reset because the stream count previously went to 0. We don't need to retain the assignment that we had backed up, so just copy off of the now clean current state assignment after the reset has occcurred with the new link_enc_cfg_copy() interface. Fixes: 6d63fcc2 ("drm/amd/display: Reset link encoder assignments for GPU reset") Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Chris Park authored
[Why] Virtualization enters blue screen of death (BSoD) due to NULL res_pool object when accessing DSC encoder capability. [How] Add NULL check to avoid blue screen of death. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Chris Park <Chris.Park@amd.com> Tested-by:
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Aric Cyr authored
drm/amd/display: 3.2.176 This version brings along following fixes: - move FPU operations from dcn21 to dml/dcn20 folder - move FPU-related code from dcn20 to dml folder - Fix compile error from TO_CLK_MGR_INTERNAL - Fix double free during GPU reset on DC streams - Add NULL check - [FW Promotion] Release 0.0.107.0 - enable dcn315/316 s0i2 support - handle DP2.0 RX with UHBR20 but not UHBR13.5 support - disable HPD SW timer for passive dongle type 1 only - add gamut coefficient set A and B - merge two duplicated clock_source_create - Add link dp trace support - move FPU associated DCN303 code to DML folder - Release AUX engine after failed acquire - Add minimal pipe split transition state - Clean up fixed VS PHY test w/a function - fix the clock source contruct for dcn315 - cleaning up smu_if to add future flexibility - fix deep color ratio - add debug option to bypass ssinfo from bios for dcn315 Acked-by: -
Anthony Koo authored
Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Charlene Liu authored
[why] enable the support in driver, let the control by CMOS Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] DP2.0 defines DP2.0 RX capability using bit maps. This means there is a corner case the DP2.0 RX can declare UHBR20 capability but not UHBR13.5 support. In this case we should skip UHBR13.5 selection and continue to our next option in decide liink settings. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Sung Joon Kim authored
[why] Need to provide this workaround only for type 1 passive dongle [how] Detect if dongle is type 1 or 2. And use it to determine if w/a is needed. Reviewed-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] Screen shake on DCN3 night light SDR BR3. [How] Change the logic to use double buffer reisgter on gamut settings. Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Jingwen Zhu <jingwen.zhu@amd.com> Tested-by:
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Charlene Liu authored
[why] dcn31x could use dcn31 sepcific which contains deep_color_ratio for dmub Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] It is nice to have link training and link loss status logging in our trace, and this patch add the all necessary accessors in dc side. [How] 1. Define dp_trace struct and create new file link_dp_trace.c and link_dp_trace.h; 2. Add dp link training status update in dc_link_dp.c; Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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Jasdeep Dhillon authored
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN303 to DML, where all FPU code should locate. Co-authored-by:
Jasdeep Dhillon <jasdeep.dhillon@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Wyatt Wood authored
[Why] There is a sequence in which aux arbitration doesn't work correctly. Driver is left with aux access after it times out waiting for access. In future dmub fw is never granted aux access and is stuck in a while loop. [How] Cancel aux request from driver after timing out. Reviewed-by:
Wyatt Wood <wyatt.wood@amd.com> Tested-by:
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Dillon Varone authored
[WHY?] When adding/removng a plane to some configurations, unsupported pipe programming can occur when moving to a new plane. [HOW?] Add a safe transistion state before programming new configuration. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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George Shen authored
[Why] Unify naming for fixed VS workarounds. [How] Rename function to match naming convention. Refactor code to remove unused function. Reviewed-by:
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Charlene Liu authored
[why] Driver sends invalid deep color ratio to DMUB. Update it to the right one by using another clock source construct. Reviewed-by:
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Leung, Martin authored
why and how: need to hook in new smu interfaces cleaning up code that used old variables Reviewed-by:
Leung, Martin <Martin.Leung@amd.com> Tested-by:
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Hansen Dsouza authored
Fix enum mapping for deep color ratio Reviewed-by:
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Charlene Liu authored
[Why & How] Add debug option to bypass ssinfo from BIOS for dcn315. Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Yifan Zhang authored
smu 13.0.5 use new registers for smu msg and param. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Lijo Lazar authored
On aldebaran, BACO dummy mode may be enabled during reset. Disable it during resume. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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- 11 Mar, 2022 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2022-03-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Reduce overzealous alignment constraints for GGTT - Add missing mdev attribute "name" for GVT - Async flip fixes (Ville) - Static checker fix (Ville) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YimvoLOZ8RPKrITv@jlahtine-mobl.ger.corp.intel.com
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- 09 Mar, 2022 6 commits
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Dave Airlie authored
Merge tag 'amd-drm-next-5.18-2022-03-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.18-2022-03-09: amdgpu: - Misc code cleanups - Misc display fixes - PSR display fixes - More RAS cleanup - Hotplug fix - Bump minor version for hotplug tests - SR-IOV fixes - GC 10.3.7 updates - Remove some firmwares which are no longer used - Mode2 reset refactor - Aldebaran fixes - Add VCN fwlog feature for VCN debugging - CS code cleanup - Fix clang warning - Fix CS clean up rebase breakage amdkfd: - SVM fixes - SMI event fixes and cleanups - vmid_pasid mapping fix for gfx10.3 Signed-off-by:
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
Follow-up pull req for v5.18 to pull in some important fixes. Signed-off-by:
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Lang Yu authored
It should be p->job->ibs[j] instead of p->job->ibs[i] here. Fixes: cdc7893f ("drm/amdgpu: use job and ib structures directly in CS parsers") Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Yifan Zhang authored
it makes no sense to continue with an undefined vmid. Fixes: c8b0507f ("drm/amdkfd: judge get_atc_vmid_pasid_mapping_info before call") Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'exynos-drm-next-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next New feature - Add BGR pixel format support for FIMD device. As for this, this patch uses undocumented register, WIN_RGB_ORDER, but it is safe because product kernels have been using same register. Signed-off-by:
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Matthew Auld authored
Currently this will enforce both 2M alignment and padding for any LMEM pages inserted into the GGTT. However, this was only meant to be applied to the compact-pt layout with the ppGTT. For the GGTT we can reduce the alignment and padding to 64K. Bspec: 45015 Fixes: 87bd701e ("drm/i915: enforce min GTT alignment for discrete cards") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Robert Beckett <bob.beckett@collabora.com> Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220303100229.839282-1-matthew.auld@intel.com (cherry picked from commit c64fa77d) Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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- 08 Mar, 2022 7 commits
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Rob Clark authored
Avoid going down devfreq paths on devices where devfreq is not initialized. v2: Change has_devfreq() logic [Dmitry] Reported-by:
Linux Kernel Functional Testing <lkft@linaro.org> Reported-by:
Anders Roxell <anders.roxell@linaro.org> Signed-off-by:
Rob Clark <robdclark@chromium.org> Fixes: 6aa89ae1 ("drm/msm/gpu: Cancel idle/boost work on suspend") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220308184844.1121029-1-robdclark@gmail.com
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Dan Carpenter authored
These casts need to happen before the shift. The only time it would matter would be if "rev.core" is >= 128. In that case the sign bit would be extended and we do not want that. Fixes: afab9d91 ("drm/msm/adreno: Expose speedbin to userspace") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Link: https://lore.kernel.org/r/20220307133105.GA17534@kiliSigned-off-by:
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https://github.com/intel/gvt-linuxJoonas Lahtinen authored
- add the missing attribute "name" in VFIO mdev hierarchy. Signed-off-by:
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Ville Syrjälä authored
The current implementation of the async flip wm0/ddb optimization does not work at all. The biggest problem is that we skip the whole intel_pipe_update_{start,end}() dance and thus never actually complete the commit that is trying to do the wm/ddb change. To fix this we need to move the do_async_flip flag to the crtc state since we handle commits per-pipe, not per-plane. Also since all planes can now be included in the first/last "async flip" (which gets converted to a sync flip to do the wm/ddb mangling) we need to be more careful when checking if the plane state is async flip comptatible. Only planes doing the async flip should be checked and other planes are perfectly fine not adhereing to any async flip related limitations. However for subsequent commits which are actually going do the async flip in hardware we want to make sure no other planes are in the state. That should never happen assuming we did our job correctly, so we'll toss in a WARN to make sure we catch any bugs here. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220214105532.13049-4-ville.syrjala@linux.intel.comReviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (cherry picked from commit 2e084371) Signed-off-by:
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Ville Syrjälä authored
Since the async flip state check is done very late and thus it can see potentially all the planes in the state (due to the wm/ddb optimization) we need to move the "can the requested plane do async flips at all?" check much earlier. For this purpose we introduce intel_async_flip_check_uapi() that gets called early during the atomic check. And for good measure we'll throw in a couple of basic checks: - is the crtc active? - was a modeset flagged? - is+was the plane enabled? Though atm all of those should be guaranteed by the fact that the async flip can only be requested through the legacy page flip ioctl. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:
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Ville Syrjälä authored
data_rate==0 no longer means a plane is disabled, it could also mean we want to use the minimum ddb allocation for it. Hence we can't bail out early during ddb allocation or else we'll simply forget to allocate any ddb for such planes. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: 6a4d8cc6 ("drm/i915: Don't allocate extra ddb during async flip for DG2") Signed-off-by:
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Ville Syrjälä authored
bigjoiner_pipes==0 leads bigjoiner_master_pipe() to do BIT(ffs(0)-1) which is undefined behaviour. The code should actually still work fine since the only place we provoke that is intel_crtc_bigjoiner_slave_pipes() and it'll bitwise AND the result with 0, so doesn't really matter what we get out of bigjoiner_master_pipe(). But best not provoke undefined behaviour anyway. Reported-by:
kernel test robot <oliver.sang@intel.com> Fixes: a6e7a006 ("drm/i915: Change bigjoiner state tracking to use the pipe bitmask") Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> (cherry picked from commit cccc71b5) Signed-off-by:
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