1. 16 Oct, 2015 1 commit
    • Tony Lindgren's avatar
      ARM: OMAP2+: Fix oops with LPAE and more than 2GB of memory · 6a3b764b
      Tony Lindgren authored
      On boards with more than 2GB of RAM booting goes wrong with things not
      working and we're getting lots of l3 warnings:
      
      WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147
      l3_interrupt_handler+0x260/0x384()
      44000000.ocp:L3 Custom Error: MASTER MMC6 TARGET DMM1 (Idle):
      Data Access in User mode during Functional access
      ...
      [<c044e158>] (scsi_add_host_with_dma) from [<c04705c8>]
      (ata_scsi_add_hosts+0x5c/0x18c)
      [<c04705c8>] (ata_scsi_add_hosts) from [<c046b13c>]
      (ata_host_register+0x150/0x2cc)
      [<c046b13c>] (ata_host_register) from [<c046b38c>]
      (ata_host_activate+0xd4/0x124)
      [<c046b38c>] (ata_host_activate) from [<c047f42c>]
      (ahci_host_activate+0x5c/0x194)
      [<c047f42c>] (ahci_host_activate) from [<c0480854>]
      (ahci_platform_init_host+0x1f0/0x3f0)
      [<c0480854>] (ahci_platform_init_host) from [<c047c9dc>]
      (ahci_probe+0x70/0x98)
      [<c047c9dc>] (ahci_probe) from [<c04220cc>]
      (platform_drv_probe+0x54/0xb4)
      
      Let's fix the issue by enabling ZONE_DMA for LPAE. Note that we need to
      limit dma_zone_size to 2GB as the rest of the RAM is beyond the 4GB limit.
      
      Let's also fix things for dra7 as done in similar patches in the TI tree
      by Lokesh Vutla <lokeshvutla@ti.com>.
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      6a3b764b
  2. 12 Oct, 2015 4 commits
    • Tony Lindgren's avatar
      Documentation: ARM: List new omap MMC requirements · d8e1f5ed
      Tony Lindgren authored
      Earlier the PBIAS regulator was optional, not so with recent
      omap_hsmmc changes. To make things easier for people with
      custom .config files, let's add minimal documentation for it
      as suggested by Russell King <rmk+kernel@arm.linux.org.uk>.
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      d8e1f5ed
    • Uwe Kleine-König's avatar
      memory: omap-gpmc: dump "before" state before first modification · fd820a1e
      Uwe Kleine-König authored
      When gpmc_cs_show_timings is called in gpmc_cs_set_timings()
      gpmc_cs_program_settings() was already run which modifies the CONFIG1
      register. So to be more useful do the "before" dump earlier.
      Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
      Acked-by: default avatarRoger Quadros <rogerq@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      fd820a1e
    • Tony Lindgren's avatar
      memory: omap-gpmc: Fix unselectable debug option for GPMC · be59b619
      Tony Lindgren authored
      Commit 63aa945b ("memory: omap-gpmc: Add Kconfig option for debug")
      added a debug option for GPMC, but somehow managed to keep it unselectable.
      
      This probably happened because I had some uncommitted changes and the
      GPMC option is selected in the platform specific Kconfig.
      
      Let's also update the description a bit, it does not mention that
      enabling the debug option also disables the reset of GPMC controller
      during the init as pointed out by Uwe Kleine-König
      <u.kleine-koenig@pengutronix.de> and Roger Quadros <rogerq@ti.com>.
      
      Fixes: 63aa945b ("memory: omap-gpmc: Add Kconfig option for debug")
      Reported-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
      Acked-by: default avatarRoger Quadros <rogerq@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      be59b619
    • Tomi Valkeinen's avatar
      ARM: dts: am57xx-beagle-x15: set VDD_SD to always-on · 7e381ec6
      Tomi Valkeinen authored
      LDO1 regulator (VDD_SD) is connected to SoC's vddshv8. vddshv8 needs to
      be kept always powered (see commit 5a0f93c6 ("ARM: dts: Add
      am57xx-beagle-x15"), but at the moment VDD_SD is enabled/disabled
      depending on whether an SD card is inserted or not.
      
      This patch sets LDO1 regulator to always-on.
      
      This patch has a side effect of fixing another issue, HDMI DDC not
      working when SD card is not inserted:
      
      Why this happens is that the tpd12s015 (HDMI level shifter/ESD
      protection chip) has LS_OE GPIO input, which needs to be enabled for the
      HDMI DDC to work. LS_OE comes from gpio6_28. The pin that provides
      gpio6_28 is powered by vddshv8, and vddshv8 comes from VDD_SD.
      
      So when SD card is not inserted, VDD_SD is disabled, and LS_OE stays
      off.
      
      The proper fix for the HDMI DDC issue would be to maybe have the pinctrl
      framework manage the pin specific power.
      
      Apparently this fixes also a third issue (copy paste from Kishon's
      patch):
      
      ldo1_reg in addition to being connected to the io lines is also
      connected to the card detect line. On card removal, omap_hsmmc
      driver does a regulator_disable causing card detect line to be
      pulled down. This raises a card insertion interrupt and once the
      MMC core detects there is no card inserted, it does a
      regulator disable which again raises a card insertion interrupt.
      This happens in a loop causing infinite MMC interrupts.
      
      Fixes: 5a0f93c6 ("ARM: dts: Add am57xx-beagle-x15")
      Cc: Kishon Vijay Abraham I <kishon@ti.com>
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Reported-by: default avatarLouis McCarthy <compeoree@gmail.com>
      Acked-by: default avatarNishanth Menon <nm@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      7e381ec6
  3. 11 Oct, 2015 8 commits
  4. 10 Oct, 2015 12 commits
  5. 09 Oct, 2015 10 commits
  6. 08 Oct, 2015 5 commits
    • Mikulas Patocka's avatar
      crash in md-raid1 and md-raid10 due to incorrect list manipulation · a452744b
      Mikulas Patocka authored
      The commit 55ce74d4 (md/raid1: ensure
      device failure recorded before write request returns) is causing crash in
      the LVM2 testsuite test shell/lvchange-raid.sh. For me the crash is 100%
      reproducible.
      
      The reason for the crash is that the newly added code in raid1d moves the
      list from conf->bio_end_io_list to tmp, then tests if tmp is non-empty and
      then incorrectly pops the bio from conf->bio_end_io_list (which is empty
      because the list was alrady moved).
      
      Raid-10 has a similar bug.
      
      Kernel Fault: Code=15 regs=000000006ccb8640 (Addr=0000000100000000)
      CPU: 3 PID: 1930 Comm: mdX_raid1 Not tainted 4.2.0-rc5-bisect+ #35
      task: 000000006cc1f258 ti: 000000006ccb8000 task.ti: 000000006ccb8000
      
           YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
      PSW: 00001000000001001111111000001111 Not tainted
      r00-03  000000ff0804fe0f 000000001059d000 000000001059f818 000000007f16be38
      r04-07  000000001059d000 000000007f16be08 0000000000200200 0000000000000001
      r08-11  000000006ccb8260 000000007b7934d0 0000000000000001 0000000000000000
      r12-15  000000004056f320 0000000000000000 0000000000013dd0 0000000000000000
      r16-19  00000000f0d00ae0 0000000000000000 0000000000000000 0000000000000001
      r20-23  000000000800000f 0000000042200390 0000000000000000 0000000000000000
      r24-27  0000000000000001 000000000800000f 000000007f16be08 000000001059d000
      r28-31  0000000100000000 000000006ccb8560 000000006ccb8640 0000000000000000
      sr00-03  0000000000249800 0000000000000000 0000000000000000 0000000000249800
      sr04-07  0000000000000000 0000000000000000 0000000000000000 0000000000000000
      
      IASQ: 0000000000000000 0000000000000000 IAOQ: 000000001059f61c 000000001059f620
       IIR: 0f8010c6    ISR: 0000000000000000  IOR: 0000000100000000
       CPU:        3   CR30: 000000006ccb8000 CR31: 0000000000000000
       ORIG_R28: 000000001059d000
       IAOQ[0]: call_bio_endio+0x34/0x1a8 [raid1]
       IAOQ[1]: call_bio_endio+0x38/0x1a8 [raid1]
       RP(r2): raid_end_bio_io+0x88/0x168 [raid1]
      Backtrace:
       [<000000001059f818>] raid_end_bio_io+0x88/0x168 [raid1]
       [<00000000105a4f64>] raid1d+0x144/0x1640 [raid1]
       [<000000004017fd5c>] kthread+0x144/0x160
      Signed-off-by: default avatarMikulas Patocka <mpatocka@redhat.com>
      Fixes: 55ce74d4 ("md/raid1: ensure device failure recorded before write request returns.")
      Fixes: 95af587e ("md/raid10: ensure device failure recorded before write request returns.")
      Signed-off-by: default avatarNeilBrown <neilb@suse.com>
      a452744b
    • Srinivas Pandruvada's avatar
      cpufreq: prevent lockup on reading scaling_available_frequencies · 55582bcc
      Srinivas Pandruvada authored
      When scaling_available_frequencies is read on an offlined cpu, then
      either lockup or junk values are displayed. This is caused by
      freed freq_table, which policy is using.
      Signed-off-by: default avatarSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      55582bcc
    • Srinivas Pandruvada's avatar
      cpufreq: acpi_cpufreq: prevent crash on reading freqdomain_cpus · e2530367
      Srinivas Pandruvada authored
      When freqdomain_cpus attribute is read from an offlined cpu, it will
      cause crash. This change prevents calling cpufreq_show_cpus when
      policy driver_data is NULL.
      
      Crash info:
      
      [  170.814949] BUG: unable to handle kernel NULL pointer dereference at 0000000000000018
      [  170.814990] IP: [<ffffffff813b2490>] _find_next_bit.part.0+0x10/0x70
      [  170.815021] PGD 227d30067 PUD 229e56067 PMD 0
      [  170.815043] Oops: 0000 [#2] SMP
      [  170.816022] CPU: 3 PID: 3121 Comm: cat Tainted: G      D    OE   4.3.0-rc3+ #33
      ...
      ...
      [  170.816657] Call Trace:
      [  170.816672]  [<ffffffff813b2505>] ? find_next_bit+0x15/0x20
      [  170.816696]  [<ffffffff8160e47c>] cpufreq_show_cpus+0x5c/0xd0
      [  170.816722]  [<ffffffffa031a409>] show_freqdomain_cpus+0x19/0x20 [acpi_cpufreq]
      [  170.816749]  [<ffffffff8160e65b>] show+0x3b/0x60
      [  170.816769]  [<ffffffff8129b31c>] sysfs_kf_seq_show+0xbc/0x130
      [  170.816793]  [<ffffffff81299be3>] kernfs_seq_show+0x23/0x30
      [  170.816816]  [<ffffffff81240f2c>] seq_read+0xec/0x390
      [  170.816837]  [<ffffffff8129a64a>] kernfs_fop_read+0x10a/0x160
      [  170.816861]  [<ffffffff8121d9b7>] __vfs_read+0x37/0x100
      [  170.816883]  [<ffffffff813217c0>] ? security_file_permission+0xa0/0xc0
      [  170.816909]  [<ffffffff8121e2e3>] vfs_read+0x83/0x130
      [  170.816930]  [<ffffffff8121f035>] SyS_read+0x55/0xc0
      ...
      ...
      [  170.817185] ---[ end trace bc6eadf82b2b965a ]---
      Signed-off-by: default avatarSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Cc: 4.2+ <stable@vger.kernel.org> # 4.2+
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      e2530367
    • ludovic.desroches@atmel.com's avatar
      mmc: sdhci-of-at91: use SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST quirk · 88c6eb0e
      ludovic.desroches@atmel.com authored
      The Atmel sdhci device needs the
      SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST quirk. Without it, the
      internal clock could never stabilised when changing the sd clock
      frequency.
      Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      88c6eb0e
    • ludovic.desroches@atmel.com's avatar
      mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST · af951761
      ludovic.desroches@atmel.com authored
      The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock
      Control Register to 0 before computing the new value and writing it.
      It disables the internal clock which causes a reset mecanism. If we
      write the new value before this reset mecanism is done, it will prevent
      the stabilisation of the internal clock, so a delay is needed. This
      delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is
      used.
      Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      af951761