- 26 Sep, 2017 40 commits
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Harry Wentland authored
We should also use it to determine pipe count. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Amy Zhang authored
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Amy Zhang <Amy.Zhang@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Corbin McElhanney authored
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Corbin McElhanney <corbin.mcelhanney@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Charlene Liu authored
DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth for the rest of the DPM levels, single channel bandwidth = 1/2 dual channel bandwidth Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Harry Wentland authored
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Andrey Grodzovsky authored
Problem : A race between two adjecent page flips makes the earlier one to release an alocated frame buffer for the subsequent one - since there are 2 frambuffer swapped back and forth between flips, the 'new' fb of the later flip is actually the 'previous' fb for the earlier flip. Fix: Don't set fb->address = 0 in cleanup hook, this is unnecessery and erases the newly cached adress that was set in prepare_fb of the second flip. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Harry Wentland authored
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Anthony Koo authored
- Add functionality to get real hw backlight level as opposed to user level, meaning the level that takes into account backlight ramping over time and backlight reduction due to Varibright - Add backlight optimization which allows for a second OS state that is able to control ABM Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Ken Chalmers authored
Not necessarily a fatal problem - some monitors will recover and show the stream anyway if link training fails. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Tony Cheng authored
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Anthony Koo authored
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Leon Elazar authored
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Leon Elazar <leon.elazar@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
If user is using DVI->HDMI dongle dual link signal might pose a problem. Keep single link signal type if clk is lower than max tmds clk. Signed-off-by:
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Andrey Grodzovsky authored
Link index is an unnecessery level of inderection when calling from kernel i2c/aux transfer into DAL. Signed-off-by:
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Harry Wentland authored
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kbuild test robot authored
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_resource.c:1085:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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kbuild test robot authored
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c:411:23-24: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c:420:39-40: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Hawking Zhang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Alex Deucher authored
Enable DCN in DC. Signed-off-by:
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Harry Wentland authored
DCN code for display interrupts. Signed-off-by:
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Harry Wentland authored
Implement support for i2c and aux on DCN. Signed-off-by:
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Harry Wentland authored
GPIOs are used for i2c and other things. Signed-off-by:
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Harry Wentland authored
Display mode lib handles clock, watermark, and bandwidth calculations for DCN. Signed-off-by:
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Harry Wentland authored
Core display support for DCN. Signed-off-by:
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Harry Wentland authored
Bandwidth and scaling calculations for DCN. Signed-off-by:
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Arindam Nath authored
There is a hard hang observed during resume from S3 when the system receives a DP short pulse interrupt. This is because there are two code paths contending for GPIO access for AUX channel transactions. One such path is through amdgpu_dm_display_resume() function which is invoked from the regular system resume code path. The other path is through handle_hpd_rx_irq(), which is invoked in response to system receiving DP short pulse interrupt. handle_hpd_rx_irq() guards against conflicting GPIO access using hpd_lock, but the GPIO access from amdgpu_dm_display_resume() remains unguarded. This patch makes sure we use hpd_lock inside amdgpu_dm_display_resume() to avoid race conditions for GPIO access. Signed-off-by:
Arindam Nath <arindam.nath@amd.com> Signed-off-by:
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Harry Wentland authored
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Hersen Wu authored
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Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Tony Cheng authored
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Yongqiang Sun authored
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Eric Cook authored
Signed-off-by:
Eric <eric.cook@amd.com> Acked-by:
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Ding Wang authored
Signed-off-by:
Ding Wang <Ding.Wang@amd.com> Acked-by:
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Eric Cook authored
-check for min/max range in freesync calculation and handle it accordingly Signed-off-by:
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