- 26 Aug, 2013 5 commits
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Maxime Ripard authored
The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Emilio López <emilio@elopez.com.ar>
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Maxime Ripard authored
The divider width used to be hardcoded. Some A31 dividers are no longer with the hardcoded width, so we need to make it specific to each divider and set it in the dividers data. Signed-off-by:
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Maxime Ripard authored
Rename all the generic-named structure to sun4i to avoid confusion when we will introduce the sun6i (A31) clocks. Signed-off-by:
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Emilio López authored
With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by:
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Maxime Ripard authored
The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by:
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- 20 Aug, 2013 3 commits
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git://git.xilinx.com/linux-xlnxMike Turquette authored
arm: Xilinx Zynq clock changes for v3.12 Just small two changes where the first fixes documentation and the second improves code readability.
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Soren Brinkmann authored
Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Soren Brinkmann authored
Signed-off-by:
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- 19 Aug, 2013 5 commits
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James Hogan authored
Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't set. This implements determine_rate for clk-mux to propagate to each parent and to choose the best one (like clk-divider this chooses the parent which provides the fastest rate <= the requested rate). The determine_rate op is implemented as a core helper function so that it can be easily used by more complex clocks which incorporate muxes. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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James Hogan authored
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by:
Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by:
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James Hogan authored
Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by:
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James Hogan authored
Move some parent related functions up in clk.c so they can be used by the modifications in the following patch which enables clock reparenting during set_rate. No other changes are made so this patch makes no functional difference in isolation. This is separate from the following patch primarily to ease readability of that patch. Signed-off-by:
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James Hogan authored
Abstract access to the clock parent cache by defining clk_get_parent_by_index(clk, index). This allows access to parent clocks from clock drivers. Signed-off-by:
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- 16 Aug, 2013 3 commits
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Mike Turquette authored
These registration calls may be used by loadable modules. Export them. Signed-off-by: -
Fabio Estevam authored
clk_register_divider() needs to be exported so that it could be used in a module driver, otherwise we get the following error: ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined! Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Stephen Boyd authored
Export this symbol so that modules can register fixed rate clocks. Signed-off-by:
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- 09 Aug, 2013 1 commit
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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- 08 Aug, 2013 15 commits
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
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Sachin Kamat authored
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by:
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Yadwinder Singh Brar authored
This patch adds support to register three(AP/CP/BT) buffered 32.768 KHz outputs of mfd-s2mps11 with common clock framework. Signed-off-by:
Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by:
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Sachin Kamat authored
'exynos5420_plls' is used only in this file. Make is static. Signed-off-by:
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Sachin Kamat authored
exynos5250_plls is used only in this file. Make it static. Signed-off-by:
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Sachin Kamat authored
'exynos4_plls' is used only in this file. Make it static. Signed-off-by:
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Fabio Estevam authored
Fix the following sparse warning: drivers/clk/mxs/clk-imx23.c:102:12: warning: symbol 'mx23_clocks_init' was not declared. Should it be static? Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Axel Lin authored
clk_register_composite() and clk_register_factors() return ERR_PTR on error. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
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Mike Turquette authored
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Sachin Kamat authored
Fixes a trivial typo. Signed-off-by:
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- 05 Aug, 2013 3 commits
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Tomasz Figa authored
This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by:
Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
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Tomasz Figa authored
This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs. Signed-off-by:
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Tomasz Figa authored
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new CLK_MUX_READ_ONLY mux flag. Signed-off-by:
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- 02 Aug, 2013 5 commits
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Vikas Sajjan authored
Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by:
Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by:
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Vikas Sajjan authored
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
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Vikas Sajjan authored
This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
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Yadwinder Singh Brar authored
This patch add set_rate() and round_rate() for PLL35xx Reviewed-by:
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Yadwinder Singh Brar authored
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by:
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