- 22 Aug, 2019 4 commits
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Xiaojie Yuan authored
Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Xiaojie Yuan authored
s/r list in rlc firmware is ready, so remove the special autoload handling Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The only place where state->max_bpc is updated on the connector is at the start of atomic check during drm_atomic_connector_check. It isn't updated when adding the connectors to the atomic state after the fact. It also doesn't necessarily reflect the right value when called in amdgpu during mode validation outside of atomic check. This can cause the wrong bpc to be used even if the max_requested_bpc is the correct value. [How] Don't rely on state->max_bpc reflecting the real bpc value and just do the min(...) based on display info bpc and max_requested_bpc. Fixes: 01933ba4 ("drm/amd/display: Use current connector state if NULL when checking bpc") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Alex Deucher authored
We need to set certain power gating flags after we determine if the firmware version is sufficient to support gfxoff. Previously we set the pg flags in early init, but we later we might have disabled gfxoff if the firmware versions didn't support it. Move adding the additional pg flags after we determine whether or not to support gfxoff. Fixes: 00544006 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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- 15 Aug, 2019 36 commits
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Andrey Grodzovsky authored
Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Add callback to call the new mode2 reset interface. Signed-off-by:
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Andrey Grodzovsky authored
Add implmenetion. Signed-off-by:
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Andrey Grodzovsky authored
Also define reset modes (0, 1 and 2) Signed-off-by:
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Andrey Grodzovsky authored
By comparing to windows it means ASIC reset. Reviewed-by:
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Andrey Grodzovsky authored
Double defintion of 'i' Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Ahzo authored
This fixes screen corruption/flickering on 75 Hz displays. v2: make print statement debug only (Alex) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646Reviewed-by:
Ahzo <Ahzo@tutanota.com> Signed-off-by:
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Gang Ba authored
When VM state changed and system in large bar mode, make sure to use CPU update function, otherwise use SDMA function. Reviewed-by:
Gang Ba <gaba@amd.com> Signed-off-by:
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Yong Zhao authored
The amdgpu_task_info will be used when printing VM page fault for KFD processes. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
Harish Kasiviswanathan <harish.kasiviswanatha@amd.com> Signed-off-by:
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Yong Zhao authored
We have done this for pre-GFX10 asics, but GFX10 did not pick up the new change. The below is the commit message for that change. This is recommended by HW designers. Previously when it was set to 1, the PDE walk error in VM fault will be treated as PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT. As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly. The above behavior is kind of abnormal. Furthermore, the PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs and it never made it way to production. Therefore, we should set it to 0. Signed-off-by:
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Yong Zhao authored
The printing we did for GFX9 was not propogated to GFX10 somehow, so fix it now. Signed-off-by:
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Yong Zhao authored
RW is also useful in most cases. Signed-off-by:
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Oak Zeng authored
Calling amdgpu function to invalidate TLB, instead of using a kfd implementation. Delete the kfd local TLB invalidation implementation. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Oak Zeng authored
This is for kfd to reuse amdgpu TLB invalidation function. On gfx10, kfd only needs to flush TLB on gfx hub but not on mm hub. So export a function for KFD flush TLB only on specific hub. Signed-off-by:
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Leo Li authored
[Why] Previous SOC bounding box firmware loading logic was for NV10, when we still had it in firmware. Now that it's brought into driver code, and NV12 BB is in firmware, this logic needs to be repurposed for NV12. [How] Set SOC_BOUNDING_BOX_VALID to false, and add the dcn_2_0_nv12_soc BB struct. In init_soc_bounding_box, load firmware to nv12 BB instead. In addition, conditionally update and patch the BB, depending on ASIC REV. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Michael Strauss authored
[Why] DCN10 performs color processing before MPC combination, causes color shift in RGB colorspaces when positive brightness offset is applied However, YCbCr is still unfixed and remains disabled [How] Add layerIndex to dc_plane_state and dc_plane_info structs Re-enable MPO when brightness is adjusted and colorspace is not YCbCr Set rear plane's brightness offset to 0 when front plane visible Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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yanyan kang authored
[why] disable_az_endpoint has been skipped because dc->debug.az_endpoint_mute_only = true. [how] set dc->debug.az_endpoint_mute_only false when PPLIB’s PME notification function pointer is not NULL at the dcn10_resource construct function,because right now SMU/PPLIB and DAL all have the AZ D3 force PME notification implemented. AZ D3 should work. Signed-off-by:
yanyan kang <Yanyan.Kang@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Wenjing Liu authored
[why] During detection link training if a display is disconnected, the current code will retry 3 times of link training on disconnected link before giving up. [how] Before each retry check for HPD status, only retry verify link cap when HPD is still high. Also put a 10ms delay between each retry to improve the chance of success. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by:
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Charlene Liu authored
Enable dcn_mem_pwr as golden setting updates Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
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Dmytro Laktyushkin authored
Currently the paremeters are extracted as if dml is calculating using pipes as we pass them in. in reality, dml internally merges pipes into planes if pipe split is detected. This change adds reverse logic to dcn20_calculate_dlg_params so that the global sync parameters can be correctly extracted for all the pipes when pipe split is enabled. Signed-off-by:
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Anthony Koo authored
Signed-off-by:
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Nikola Cornij authored
[why] Some logs messages were not precise and some new log messages were needed after "get packed PPS" function was introduced Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] A recent bug showed that logging would be useful in debugging various gamma issues. [How] Add logging in dc. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Julian Parkin authored
There are repeated (but guarded) definitions of dwb_src enums. There are also unused entires. Clean them up. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
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Qingqing Zhuo authored
Add h_timing_div_mode enum to better reflect possible register values. Replace previously programmed values with enum Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] These are needed to send back DRM vblank events in the case where VRR is on. Without the interrupt enabled we're deferring the events into the vblank queue and userspace is left waiting forever to get back the events they need. Found using igt@kms_vrr - the test fails immediately due to vblank timeout. [How] Register them the same way we're handling it for DCN1. This fixes igt@kms_vrr for DCN2. Signed-off-by:
David Francis <David.Francis@amd.com> Acked-by:
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Charlene Liu authored
[Description] OGAM_MEM_PWR could stay in light up when driver woke up to update gamma. either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away. Easy reproduce after LOW_MEM Power feature enables and resume from S3. Signed-off-by:
Julian Parkin <jparkin@amd.com> Acked-by:
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Nikola Cornij authored
[why] A misleading message "Programming PPS" appears before both programming and "query PPS" functions [how] Move the message from "log PPS" function to "program PPS" function Signed-off-by:
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Vitaly Prosyak authored
Not all ASIC types have this function implemented - check before calling. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Ilya Bakoulin authored
The type was changed previously to better reflect possible register values. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] A recent bug showed that logging would be useful in debugging various gamma issues. [How] Add new log types and logging code to the color module. Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Nikola Cornij authored
[why] If DSC is available, a higher picture quality is achieved by using DSC with 4:4:4 format. Using 4:2:2 instead does not offer any benefit and would only introduce loss of quality. Removing it reduces maintenance and testing effort. Signed-off-by:
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Lewis Huang authored
[Why] The vm config will be clear to 0 when system enter S4. It will cause hubbub didn't know how to fetch data when system resume. The flip always pending because earliest_inuse_address and request_address are different. [How] Reprogram VM config when system resume Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Eric Yang authored
[Why and How] We want to change where timing is done for alt mode. Some of the commented out #ifs are needed for DCN20 so we enable them for that case. Signed-off-by:
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Ilya Bakoulin authored
[Why] - Need to change interface function signature / add an enum to reflect the available register field values [How] - Add a new enum and modify existing functions to use it instead of bool Signed-off-by:
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