- 15 May, 2018 40 commits
-
-
Samuel Li authored
Enables sg display if vram size <= THRESHOLD(256M); otherwise still use vram as display buffer. This patch fixed some potention issues introduced by change "allow framebuffer in GART memory as well" due to CZ/ST hardware limitation. v2: Change default setting to auto. v3: Move some logic from amdgpu_display_framebuffer_domains() to pin function, suggested by Christian. v4: Split into several patches. v5: Drop module parameter for now. Signed-off-by:Samuel Li <Samuel.Li@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
-
Alex Deucher authored
Set query to the power value so we actually return it. Fixes no power value returned on asics with the new query. Tested-by:
Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
-
Rex Zhu authored
when user cat pp_od_clk_voltage add display info about the sclk/mclk/vddc range that user can overdrive output as: OD_SCLK: 0: 300MHz 900mV 1: 400MHz 912mV 2: 500MHz 925mV 3: 600MHz 937mV 4: 700MHz 950mV 5: 800MHz 975mV 6: 900MHz 987mV 7: 1000MHz 1000mV OD_MCLK: 0: 300MHz 900mV 1: 1500MHz 912mV OD_RANGE: SCLK: 300MHz 1200MHz MCLK: 300MHz 1500MHz VDDC: 700mV 1200mV also 1. remove unnecessary whitespace before a quoted newline 2. change unit of frequency Mhz to MHz Reviewed-by:
-
Rex Zhu authored
read vddc range from vbios. Reviewed-by:
-
Rex Zhu authored
if vddc restore to default value, driver clear the bit of DPMTABLE_OD_UPDATE_VDDC and need to repopulate sclk and mclk table. 1. Remove variable i checking code. 2. move clear DPMTABLE_OD_UPDATE_VDDC bit to the end of the function to avoid sclk table will not be updated. Reviewed-by:
-
Rex Zhu authored
Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
-
Rex Zhu authored
to keep consistent with other asics Reviewed-by:
-
Alex Deucher authored
sysfs interface for fine grained clock and voltage control. Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
-
Alex Deucher authored
sysfs file for adjusting power level heuristics. Acked-by:
-
Alex Deucher authored
Used for manually masking dpm states. v2: drop comment about current state (Rex) Acked-by:
-
Alex Deucher authored
This file is for uploading new powerplay tables. Acked-by:
-
Alex Deucher authored
This is a legacy file and is only provided for backwards compatibility. Acked-by:
-
Alex Deucher authored
Provide documentation for power_dpm_force_performance_level which is used to adjust things related to GPU power states. Acked-by:
-
Samuel Li authored
This fixes an issue introduced by change "allow framebuffer in GART memory as well" which could lead to a shared buffer ending up pinned in vram. Use GTT if it is included in the domain, otherwise return an error. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Samuel Li authored
It returns supported domains for display, and domains actually used are to be decided later when pinned. Signed-off-by:
-
Huang Rui authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
We need enable CGPG and GFXOFF together. If only enable one of them, this system will get hang after startx (do draw command). So when gfxoff is disabled, it also need disable CGPG after that. Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
gfx_off_control is used to be called for sending enabling/disabling gfxoff message. Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
It will be used not only for powerplay but also on amdgpu part in future patches. So move it into amd_shared header file. Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
drm/amdgpu: revise init_rlc_save_restore_list behavior to support latest register_list_format/register_restore table RLC save/restore list will be used on CGPG and GFXOFF function, it loads two bin table of register_list_format/register_restore in RLC firmware. Signed-off-by:
-
Huang Rui authored
Remove gfx_v9_0_enable_sck_slow_down_on_power_up/down and CP power gating enabling functions because they only need to be called on setting power gating behavior. We keep it in set_powergating callback to enable/disable PG in late_init. Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
RLC save/restore list cntl/gpm_mem/srm_mem ucodes are used for CGPG and gfxoff function. Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Huang Rui authored
Signed-off-by:
-
Kenneth Feng authored
For the dummy ACG fuses,need to disable ACG, otherwise corruption will be caused. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
-
Christian König authored
Just note if a BO was imported/exported. Signed-off-by:
-
Kenneth Feng authored
update vega12 smu interface. Signed-off-by:
-
Junwei Zhang authored
v2: fix compiling warning Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
-
Flora Cui authored
fix settings. Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
-
