- 25 Jun, 2024 4 commits
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Krzysztof Kozlowski authored
Regex for newer Adreno compatibles can be simpler. Suggested-by:
Conor Dooley <conor@kernel.org> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Patchwork: https://patchwork.freedesktop.org/patch/600505/ Link: https://lore.kernel.org/r/20240623-qcom-adreno-dts-bindings-driver-v2-3-9496410de992@linaro.orgSigned-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Krzysztof Kozlowski authored
All devices should (and actually do) have same order of entries, if possible. That's the case for reg/reg-names, so define the reg-names in top-level to enforce that. Acked-by:
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Krzysztof Kozlowski authored
We expect each schema with variable number of clocks, to have the widest constrains in top-level "properties:". This is more readable and also makes binding stricter, if there is no "if:then:" block for given variant. Acked-by:
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Dmitry Baryshkov authored
The frame event callback is always set to dpu_crtc_frame_event_cb() (or to NULL) and the data is always either the CRTC itself or NULL (correpondingly). Thus drop the event callback registration, call the dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc assigned using dpu_encoder_assign_crtc(). Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/600751/ Link: https://lore.kernel.org/r/20240625-dpu-no-crtc-register-v3-1-1b161df13776@linaro.org
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- 24 Jun, 2024 15 commits
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Daniil Titov authored
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only difference from existing msm8916 configuration is number of phy and io_start addresses. Signed-off-by:
Daniil Titov <daniilt971@gmail.com> Reviewed-by:
Barnabás Czémán <trabarni@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600518/ Link: https://lore.kernel.org/r/20240623-dsi-v2-4-a0ca70fb4846@gmail.comSigned-off-by:
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Barnabás Czémán authored
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Daniil Titov authored
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937. Signed-off-by:
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Barnabás Czémán authored
Add the compatible for the MDP5 found on MSM8937. Reviewed-by:
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Barnabás Czémán authored
Remove MDP_CAP_SRC_SPLIT from msm8x53_config because it is not referenced in downstream. Fixes: fb25d447 ("drm/msm/mdp5: Add configuration for MDP v1.16") Signed-off-by:
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Jani Nikula authored
Prefer the struct drm_edid based functions for reading the EDID and updating the connector. Simplify the flow by updating the EDID property when the EDID is read instead of at .get_modes. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/593976/ Link: https://lore.kernel.org/r/93d6c446ed4831dadfb4a77635a67cf5f27e19ff.1715691257.git.jani.nikula@intel.comSigned-off-by:
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Barnabás Czémán authored
CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts, so better to skip CTL irq callback register/unregister make dpu_ctl_cfg be able to define without intr_start. Signed-off-by:
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Dmitry Baryshkov authored
Rename dpu_hw_setup_vsync_source functions to make the names match the implementation: on DPU 5.x the TOP only contains timer setup, while 3.x and 4.x used MDP_VSYNC_SEL register to select TE source. Signed-off-by:
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Dmitry Baryshkov authored
Make the DPU driver use the TE source specified in the DT. If none is specified, the driver defaults to the first GPIO (mdp_vsync_p). Signed-off-by:
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Dmitry Baryshkov authored
Allow board's device tree to specify the vsync source (aka TE source). If the property is omitted, the display controller driver will use the default setting. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598740/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-6-67a0116b5366@linaro.org
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Dmitry Baryshkov authored
The struct msm_display_info has is_te_using_watchdog_timer field which is neither set anywhere nor is flexible enough to specify different sources. Replace it with the field specifying the vsync source using enum dpu_vsync_source. Reviewed-by:
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Dmitry Baryshkov authored
Setting vsync source makes sense only for DSI CMD panels. Pull the is_cmd_mode condition out of the function into the calling code, so that it becomes more explicit. Reviewed-by:
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Dmitry Baryshkov authored
Neither disp-enable-gpios nor disp-te-gpios are defined in the schema. None of the board DT files use those GPIO pins. Drop them from the driver. Reviewed-by:
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Dmitry Baryshkov authored
Add enum dpu_vsync_source instead of a series of defines. Use this enum to pass vsync information. Reviewed-by:
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Dmitry Baryshkov authored
Command mode panels provide TE signal back to the DSI host to signal that the frame display has completed and update of the image will not cause tearing. Usually it is connected to the first GPIO with the mdp_vsync function, which is the default. In such case the property can be skipped. Acked-by:
Rob Herring (Arm) <robh@kernel.org> Signed-off-by:
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- 23 Jun, 2024 5 commits
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Abhinav Kumar authored
clear_pending_flush() ctl op is always assigned irrespective of the DPU hardware revision. Hence there is no needed to check whether the op has been assigned before calling it. Drop the checks across the driver for clear_pending_flush() and also update its documentation that it is always expected to be assigned. changes in v2: - instead of adding more validity checks just drop the one for clear_pending_flush - update the documentation for clear_pending_flush() ctl op - update the commit text reflecting these changes changes in v3: - simplify the documentation of clear_pending_flush Fixes: d7d0e73f ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/464fbd84-0d1c-43c3-a40b-31656ac06456@moroto.mountain/T/Signed-off-by:
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Danila Tikhonov authored
Add support for MDSS on SM7150. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
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Danila Tikhonov authored
Document the MDSS hardware found on the Qualcomm SM7150 platform. Signed-off-by:
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Danila Tikhonov authored
Add definitions for the display hardware used on the Qualcomm SM7150 platform. Signed-off-by:
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Danila Tikhonov authored
Document the DPU hardware found on the Qualcomm SM7150 platform. Signed-off-by:
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- 22 Jun, 2024 8 commits
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Jonathan Marek authored
Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Reviewed-by:
Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596236/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-6-2ab1d334c657@linaro.orgSigned-off-by:
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Jonathan Marek authored
Video mode DSC won't work if this field is not set correctly. Set it to fix video mode DSC (for slice_per_pkt==1 cases at least). Fixes: 08802f51 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by:
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Jonathan Marek authored
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the driver is doing in video mode. Fix that by actually enabling widebus for video mode. Fixes: efcbd6f9 ("drm/msm/dsi: Enable widebus for DSI") Signed-off-by:
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Jun Nie authored
Enable compression bit in cfg2 register for DSC in the DSI case per hardware version. Signed-off-by:
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Jun Nie authored
data is valid for only half the active window if widebus is enabled Signed-off-by:
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Jonathan Marek authored
Add width change in DPU timing for DSC compression case to work with DSI video mode. Signed-off-by:
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Konrad Dybcio authored
These are dummy wrappers that do literally nothing interesting. Remove them. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
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Konrad Dybcio authored
These are dummy wrappers that do literally nothing interesting. Remove them. Signed-off-by:
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- 21 Jun, 2024 7 commits
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Connor Abbott authored
This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by:
Connor Abbott <cwabbott0@gmail.com> Reviewed-by:
Rob Clark <robdclark@chromium.org>
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Connor Abbott authored
Expose the value of the software fuse to userspace. Reviewed-by:
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Connor Abbott authored
On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled. Reviewed-by:
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Connor Abbott authored
This will used by drm/msm to initialize GPU registers that Qualcomm's firmware doesn't make writeable to the kernel. Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/592039/Signed-off-by:
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Rob Clark authored
This should allow disabling the zap node via an overlay, for slbounce. Suggested-by:
Nikita Travkin <nikita@trvn.ru> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/594572/
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Rob Clark authored
When debugging faults, it is useful to know how the BO is mapped (cached vs WC, gpu readonly, etc). Signed-off-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Acked-by:
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Rob Clark authored
Perfetto can use these traces to track global and per-process GPU memory usage. Signed-off-by:
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- 20 Jun, 2024 1 commit
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Konrad Dybcio authored
UBWC_MODE is a one-bit-wide field, so a value of 2 is obviously bogus. Replace it with the correct value (0). Fixes: 18397519 ("drm/msm/adreno: Add A702 support") Reported-by:
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