- 28 Oct, 2021 32 commits
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Aric Cyr authored
Acked-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Anthony Koo authored
- Add flag to control root clock gating in init_hw - Add flag to indicate a diags environment is being used Acked-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Aric Cyr authored
[Why] When writing long AUX commands some sinks will respond will write status update requiring source to read status. [How] When a write request is replied with data (AUX_ACK_M), retry a read of write status to determine when the write is completed. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Tested-by:
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George Shen authored
[Why] Currently the naming of preferred_training_settings is ambiguous and has caused confusion regarding its purpose and usage. [How] Add comment to clarify the intention. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Tested-by:
George Shen <george.shen@amd.com> Signed-off-by:
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George Shen authored
[Why] Currently there are use cases that require DP link to maintain fixed VS and PE in HW regardless of what the sink requests. BIOS integrated info table will specify whether we need to use the fixed drive settings, and the drive settings to use. [How] Implement changes to parse the integrated info table and set the fixed drive settings accordingly. Reviewed-by:
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Dmytro Laktyushkin authored
Style change for better consistency across codebase Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Tested-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
This is unnecessary in clk_mgr Reviewed-by:
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Michael Strauss authored
[WHY] Every other CM LUT power down sequence is deferred to next vupdate as memory powerdown updates immediately while selecting LUTs is double buffered. Previous update to defer LUT power down missed GAMCOR and DSCL, causing some visible flicker when entering/exiting fullscreen video playback. [HOW] Update dpp deferred update loop to check for valid DPPs in res_pool instead of referencing dcn_ip which turns out to not be populated during runtime. Move GAMCOR and DSCL powerdown to dpp deferred updates. Reviewed-by:
Haonan Wang <Haonan.Wang2@amd.com> Tested-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] i2c memory doesn't get set to light sleep on hw init as intended [HOW] Set i2c to light sleep after reg gets zeroed, ensuring memory power control doesn't get disabled for any other DIO memory Reviewed-by:
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Ahmad Othman authored
[Why] Crash when USB4 is connected. [How] Added an ASIC specific code guard. Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Reviewed-by:
Ahmad Othman <Ahmad.Othman@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Ahmad Othman authored
[Why] Created new fields that matches new B0 structs On DCN31 the mapping of DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this new mapping needed to be handled. [How] Mapped new structure based on new structs Added logic for mapping over A0 and B0 boards Hooked all new structs together. Reviewed-by:
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Robin Chen authored
[Why] To expose new power optimization flags to PSR interface. It allows the PSR related power features can be enabled separately base on different use scenarios. Reviewed-by:
Robin Chen <po-tchen@amd.com> Signed-off-by:
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Guo, Bing authored
Updating certain variable blanking calculations to use ceiling function. Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
Bing Guo <Bing.Guo@amd.com> Signed-off-by:
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Anson Jacob authored
Limit when FPU is enabled to only functions that does FPU operations for dcn20_resource_construct, which gets called during driver initialization. Enabling FPU operation disables preemption. Sleeping functions(mutex (un)lock, memory allocation using GFP_KERNEL, etc.) should not be called when preemption is disabled. Fixes the following case caught by enabling CONFIG_DEBUG_ATOMIC_SLEEP in kernel config [ 1.338434] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:281 [ 1.347395] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 197, name: systemd-udevd [ 1.356356] CPU: 7 PID: 197 Comm: systemd-udevd Not tainted 5.13.0+ #3 [ 1.356358] Hardware name: System manufacturer System Product Name/PRIME X570-PRO, BIOS 3405 02/01/2021 [ 1.356360] Call Trace: [ 1.356361] dump_stack+0x6b/0x86 [ 1.356366] ___might_sleep.cold+0x87/0x98 [ 1.356370] __might_sleep+0x4b/0x80 [ 1.356372] mutex_lock+0x21/0x50 [ 1.356376] smu_get_uclk_dpm_states+0x3f/0x80 [amdgpu] [ 1.356538] pp_nv_get_uclk_dpm_states+0x35/0x50 [amdgpu] [ 1.356711] init_soc_bounding_box+0xf9/0x210 [amdgpu] [ 1.356892] ? create_object+0x20d/0x340 [ 1.356897] ? dcn20_resource_construct+0x46f/0xd30 [amdgpu] [ 1.357077] dcn20_resource_construct+0x4b1/0xd30 [amdgpu] ... Tested on: 5700XT (NAVI10 0x1002:0x731F 0x1DA2:0xE410 0xC1) Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] When the vbios config and driver config are different, if we update clock to lower before call program_timing and program_pixel_clk, garbage appear. [How] Align bw context with hw config when system resume Reviewed-by:
Lewis Huang <Lewis.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
For asics without a callback, use the current level rather than 0xff. This can avoid an unnecesary forced level set on older asics when set by the user. Reviewed-by:
Kevin Wang <kevinyang.wang@amd.com> Signed-off-by:
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Alex Deucher authored
Stutter mode is a power saving feature on GPUs, however at least one early raven system exhibits stability issues with it. Add a quirk to disable it for that system. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214417 Fixes: 00544006 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Tao Zhou authored
Remove GPRs init for ALDEBARAN in gpu reset temporarily, will add the init once the algorithm is stable. v2: Only remove GPRs init in gpu reset. v3: Suspend needs it, only skip it in gpu reset. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lang Yu authored
Actually, cu_mask has been copied to mqd memory and does't have to persist in queue_properties. Remove it from queue_properties. And use struct mqd_update_info to store such properties, then pass it to update queue operation. v2: * Rename pqm_update_queue to pqm_update_queue_properties. * Rename struct queue_update_info to struct mqd_update_info. * Rename pqm_set_cu_mask to pqm_update_mqd. Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
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Lang Yu authored
Currently, queue is updated with data in queue_properties. And all allocated resource in queue_properties will not be freed until the queue is destroyed. But some properties(e.g., cu mask) bring some memory management headaches(e.g., memory leak) and make code complex. Actually they have been copied to mqd and don't have to persist in queue_properties. Add an argument into update queue to pass such properties, then we can remove them from queue_properties. v2: Don't use void *. Suggested-by:
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Tao Zhou authored
Skip GPRs init in specific condition since current GPRs init algorithm only works for some CU settings. Signed-off-by:
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Candice Li authored
TA version should only be displayed in firmware version column. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Lang Yu authored
amdgpu_fence_driver_sw_fini() should be executed before amdgpu_device_ip_fini(), otherwise fence driver resource won't be properly freed as adev->rings have been tore down. Fixes: 72c8c97b ("drm/amdgpu: Split amdgpu_device_fini into early and late") Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Lang Yu authored
Currently, all kfd BOs use same destruction routine. But pinned BOs are not unpinned properly. Separate them from general routine. v2 (Felix): Add safeguard to prevent user space from freeing signal BO. Kunmap signal BO in the event of setting event page error. Just kunmap signal BO to avoid duplicating the code. Signed-off-by:
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Philip Yang authored
The userptr can be unmapped by application and still registered to driver, restore userptr work return user pages will get -EFAULT bad address error. Pretend this error as succeed. GPU access this userptr will have VM fault later, it is better than application soft hangs with stalled user mode queues. v2: squash in warning fix (Alex) Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Kent Russell authored
When a GPU hits the bad_page_threshold, it will not be initialized by the amdgpu driver. This means that the table cannot be cleared, nor can information gathering be performed (getting serial number, BDF, etc). If the bad_page_threshold kernel parameter is set to -2, continue to initialize the GPU, while printing a warning to dmesg that this action has been done v2: squash in Luben's fix to restore RAS info reporting Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Mukul Joshi <Mukul.Joshi@amd.com> Signed-off-by:
Kent Russell <kent.russell@amd.com> Acked-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Kent Russell authored
dmesg doesn't warn when the number of bad pages approaches the threshold for page retirement. WARN when the number of bad pages is at 90% or greater for easier checks and planning, instead of waiting until the GPU is full of bad pages. Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Mukul Joshi <Mukul.Joshi@amd.com> Signed-off-by:
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Laurent Pinchart authored
Add FourCCs for 10- and 12-bit red formats with padding to 16 bits. They correspond to the V4L2 10- and 12-bit greyscale (V4L2_PIX_FMT_Y10 and V4L2_PIX_FMT_Y12) formats, as well as the Bayer formats with the same bit depth (V4L2_PIX_FMT_SBGGR{10,12} and all other Bayer pattern permutations). These formats are not used by any kernel driver at this point, but need to be exposed to applications by libcamera, which uses DRM FourCCs for pixel formats. Signed-off-by:Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211027233140.12268-1-laurent.pinchart@ideasonboard.com
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
* eDP support in DP sub-driver (for newer SoCs with native eDP output) * dpu irq handling cleanup * CRC support for making igt happy * Support for NO_CONNECTOR bridges * dsi: 14nm phy support for msm8953 * mdp5: support for msm8x53, sdm450, sdm632 * various smaller fixes and cleanups Signed-off-by:
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Dave Airlie authored
The msm next tree is based on rc3, so let's just backmerge rc7 before pulling it in. Signed-off-by: -
Dave Airlie authored
Merge tag 'topic/amdgpu-dp2.0-mst-2021-10-27' of git://anongit.freedesktop.org/drm/drm-misc into drm-next UAPI Changes: Nope! Cross-subsystem Changes: drm_dp_update_payload_part1() takes a new argument for specifying what the VCPI slot start is Core Changes: Make the DP MST helpers aware of the current starting VCPI slot/VCPI total slot count... Driver Changes: ...and then add support for taking advantage of this for 128b/132b links on DP 2.0 for amdgpu Signed-off-by:
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- 27 Oct, 2021 2 commits
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Alex Deucher authored
Need to guard some things with CONFIG_DRM_AMD_DC_DCN. Fixes: 41724ea2 ("drm/amd/display: Add DP 2.0 MST DM Support") Signed-off-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.16-2021-10-22' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.16-2021-10-22: amdgpu: - PSP fix for resume - XGMI fixes - Interrupt fix in device tear down - Renoir USB-C DP alt mode fix for resume - DP 2.0 fixes - Yellow Carp display fixes - Misc display fixes - RAS fixes - IP Discovery enumeration fixes - VGH fixes - SR-IOV fixes - Revert ChromeOS workaround in display code - Cyan Skillfish fixes amdkfd: - Fix error handling in gpu memory allocation - Fix build warnings with some configs - SVM fixes Signed-off-by:
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- 26 Oct, 2021 6 commits
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Arnd Bergmann authored
Some randconfig builds fail when drm/drm_bridge.h is not included implicitly in this file: drivers/gpu/drm/msm/dp/dp_parser.c:279:25: error: implicit declaration of function 'devm_drm_panel_bridge_add' [-Werror,-Wimplicit-function-declaration] parser->panel_bridge = devm_drm_panel_bridge_add(dev, panel); Fixes: 4b296d15 ("drm/msm/dp: Allow attaching a drm_panel") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211026083254.3396322-1-arnd@kernel.orgSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Nathan Chancellor authored
Clang warns: drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:162:6: error: variable 'commit' is uninitialized when used here [-Werror,-Wuninitialized] if (commit) ^~~~~~ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:106:32: note: initialize the variable 'commit' to silence this warning struct drm_crtc_commit *commit; ^ = NULL 1 error generated. The assignment and use of commit in the main body of dpu_crtc_set_crc_source() were removed from v1 to v2 but the call to drm_crtc_commit_put() at the end was not. Do that now so there is no more warning. Fixes: 78d9b458 ("drm/msm/dpu: Add CRC support for DPU") Link: https://github.com/ClangBuiltLinux/linux/issues/1493Reported-by:"kernelci.org bot" <bot@kernelci.org> Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20211026142435.3606413-1-nathan@kernel.orgSigned-off-by:
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Bhawanpreet Lakha authored
[Why] Add DP2 MST and debugfs support [How] Update the slot info based on the link encoding format Reviewed-by:
"Lin, Wayne" <Wayne.Lin@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Fangzhi Zuo authored
[Why] configure/call DC interface for DP2 mst support. This is needed to make DP2 mst work. [How] - add encoding type, logging, mst update/reduce payload functions Use the link encoding to determine the DP type (1.4 or 2.0) and add a flag to dc_stream_update to determine whether to increase/reduce payloads. v2: * add DP_UNKNOWN_ENCODING handling Signed-off-by:
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Bhawanpreet Lakha authored
8b/10b encoding format requires to reserve the first slot for recording metadata. Real data transmission starts from the second slot, with a total of available 63 slots available. In 128b/132b encoding format, metadata is transmitted separately in LLCP packet before MTP. Real data transmission starts from the first slot, with a total of 64 slots available. v2: * Move total/start slots to mst_state, and copy it to mst_mgr in atomic_check v3: * Only keep the slot info on the mst_state * add a start_slot parameter to the payload function, to facilitate non atomic drivers (this is a temporary workaround and should be removed when we are moving out the non atomic driver helpers) v4: *fixed typo and formatting v5: (no functional changes) * Fixed formatting in drm_dp_mst_update_slots() * Reference mst_state instead of mst_state->mgr for debugging info Signed-off-by:
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Bhawanpreet Lakha authored
This code path is used during commit, and we dont expect things to fail during the commit stage, so remove this. Signed-off-by:
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