1. 09 Feb, 2016 2 commits
    • Josh Cartwright's avatar
      ARM: zynq: address L2 cache data corruption · 6ded93a1
      Josh Cartwright authored
      The Zynq has a bug where the L2 cache will return invalid data in some
      circumstances unless the L2C_RAM register is set to 0x00020202 before the first
      enabling of the L2 cache.
      
      The Xilinx-recommended solution to this problem is to ensure that early one of
      the earlier bootstages correctly initialize L2C_RAM, however, this issue wasn't
      discovered and fixed until after their EDK/SDK 14.4 release.  For systems built
      prior to that, and which lack field-upgradable bootloaders, this issue still
      exists and silent data corruption can be seen in the wild.
      
      Fix these systems by ensuring L2C_RAM is properly initialized at the
      earliest convenient moment prior to the L2 being brought up, which is
      when the SLCR is first mapped.
      
      The Zynq bug is described in more detail by Xilinx AR# 54190 as quoted
      below.
      
      Xilinx AR# 54190
      http://www.xilinx.com/support/answers/54190.htm
      Captured on 2014-09-24 14:43 -0500
      
        = Description =
        For proper L2 cache operation, the user code must program the
        slcr.L2C_RAM register (address 0xF800_0A1C) to the value of
        0x0002_0202 before enabling the L2 cache. The reset value
        (0x0001_0101) might cause, very infrequently, the L2 cache to return
        invalid data.
      
        = Solution =
        It is up to the user code (FSBL or other user code) to set the
        slcr.L2C_RAM register to the value 0x0002_0202 before enabling the L2
        cache.
      
        Note: The L2 cache is disabled after reset and is not enabled by the
        BootROM.
      
        Note: The slcr.l2C_RAM register was previously reserved. It is added
        in the Zynq-7000 AP SoC Technical Reference Manual (TRM) v1.5 as
        "Reserved".
      
      Thanks to Jaeden Amero for initial debugging and triage efforts.
      Signed-off-by: default avatarJosh Cartwright <joshc@ni.com>
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      6ded93a1
    • Josh Cartwright's avatar
      ARM: zynq: initialize slcr mapping earlier · 9388187f
      Josh Cartwright authored
      In preparation for performing additional configuration prior to bringing
      up L2, move the slcr initialization earlier in the boot process.
      Signed-off-by: default avatarJosh Cartwright <joshc@ni.com>
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      9388187f
  2. 24 Jan, 2016 38 commits