- 05 Dec, 2020 2 commits
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Srinivas Kandagatla authored
Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org [Add some dependencies] Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Srinivas Kandagatla authored
Add device tree binding Documentation details for Qualcomm SM8250 LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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- 04 Dec, 2020 7 commits
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Vinod Koul authored
PM55 pmic support gpio controller so add compatible and comment for gpio holes Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
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Vinod Koul authored
Add support for the PMX55 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by:
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Zou Wei authored
Fix the following sparse warnings: drivers/pinctrl/pinctrl-microchip-sgpio.c:63:31: warning: symbol 'properties_luton' was not declared. Should it be static? drivers/pinctrl/pinctrl-microchip-sgpio.c:68:31: warning: symbol 'properties_ocelot' was not declared. Should it be static? drivers/pinctrl/pinctrl-microchip-sgpio.c:73:31: warning: symbol 'properties_sparx5' was not declared. Should it be static? Signed-off-by:
Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1606218173-3722-1-git-send-email-zou_wei@huawei.comSigned-off-by:
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Tiezhu Yang authored
If CONFIG_HAS_IOMEM is not set, devm_platform_ioremap_resource() will be not built in drivers/base/platform.c and then there exists a build error about undefined reference to "devm_platform_ioremap_resource" in pinctrl-at91-pio4.c under COMPILE_TEST and CONFIG_PINCTRL_AT91PIO4, make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix it. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Link: https://lore.kernel.org/r/1606209423-4742-1-git-send-email-yangtiezhu@loongson.cnSigned-off-by:
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Zhiyong Tao authored
This patch is used to fix low level output voltage issue. A pin is changed from input pull-up to output high. The Dout value of the pin is default as 0. If we change the direction of the pin before the dout value of the pin, It maybe produce a low level output voltage between "input pull-up" and "output high". Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20201120093058.7248-2-zhiyong.tao@mediatek.comSigned-off-by:
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Yu Kuai authored
if of_find_device_by_node() succeed, pinctrl_falcon_probe() doesn't have a corresponding put_device(). Thus add put_device() to fix the exception handling for this function implementation. Fixes: e316cb2b ("OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC") Signed-off-by:
Yu Kuai <yukuai3@huawei.com> Link: https://lore.kernel.org/r/20201119011219.2248232-1-yukuai3@huawei.comSigned-off-by:
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Cristian Ciocaltea authored
s500_padinfo[] is never modified and should be made 'const' to allow the compiler to optimize code generation, i.e. put it in the text section instead of the data section. Before: text data bss dec hex filename 12503 5088 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o After: text data bss dec hex filename 14435 3156 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Link: https://lore.kernel.org/r/24505deb08d050eb4ce38f186f4037d7541ea217.1605722628.git.cristian.ciocaltea@gmail.comSigned-off-by:
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- 01 Dec, 2020 5 commits
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Lars Povlsen authored
The pinctrl-microchip-sgpio driver needs OF support, so add that to Kconfig. Reported-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Acked-by:
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Lars Povlsen authored
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO (SGPIO) device used in various SoC's. The driver is added as a pinctrl driver, albeit only having just GPIO support currently. The hardware supports other functions that will be added following. Signed-off-by:
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Lars Povlsen authored
This adds DT bindings for the Microsemi/Microchip SGPIO controller, bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and mscc,luton-sgpio. Signed-off-by:
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Linus Walleij authored
Merge tag 'samsung-pinctrl-5.11' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v5.11 Only a cleanup of unneeded breaks.
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.11 (take two) - Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N, - A small fix for a Clang warning.
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- 24 Nov, 2020 8 commits
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Eugen Hristev authored
Some products, like sama7g5, do not have a full last bank of PIO lines. In this case for example, sama7g5 only has 8 lines for the PE bank. PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines. To cope with this situation, added a data attribute that is product dependent, to specify the number of lines of the last bank. In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK, adjust the total number of lines accordingly. This will avoid advertising 160 lines instead of the actual 136, as this product supports, and to avoid reading/writing to invalid register addresses. Signed-off-by:
Eugen Hristev <eugen.hristev@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.comSigned-off-by:
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.11-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.11-1 * Add Intel Alder Lake-S pin controller support * Add Intel Elkhart Lake pin controller support * Add Intel Lakefield driver pin controller support * Miscellaneous fixes for Intel Lynxpoint driver The following is an automated git shortlog grouped by driver: intel: - Add Intel Alder Lake-S pin controller support - Add Intel Elkhart Lake pin controller support - Add blank line before endif in Kconfig - Add Intel Lakefield pin controller support lynxpoint: - Enable pin configuration setting for GPIO chip - Use defined constant for disabled bias explicitly - Unify initcall location in the code
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Yangtao Li authored
It is found on many allwinner soc that there is a low probability that the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This will cause the interrupt status of a gpio bank to always be active on gic, preventing gic from responding to other spi interrupts correctly. So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler(). Signed-off-by:
Yangtao Li <frank@allwinnertech.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.comSigned-off-by:
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Yangtao Li authored
The interrupt descriptor cannot be found in the interrupt processing function, and this situation cannot happen when the system is running normally. It doesn't seem right to return directly to the status of not handling gic. In this case, it must be a bug, let's mark it with WARN_ON. Signed-off-by:
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Yangtao Li authored
A100's pin starts with PB, so it should start with 1. Fixes: 473436e7 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller") Signed-off-by:
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Rajendra Nayak authored
Add initial pinctrl driver to support pin configuration with pinctrl framework for SC7280 SoC Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
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Rajendra Nayak authored
Add device tree binding Documentation details for Qualcomm SC7280 TLMM block. Signed-off-by:
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John Stultz authored
One fixup following my patch commit be117ca3 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a selected config") being queued in LinusW's tree, as a new config entry was added for the msm8953 that also needs the change. Applies to LinusW's pinctrl devel tree. Signed-off-by:
John Stultz <john.stultz@linaro.org> Reviewed-by:
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- 23 Nov, 2020 6 commits
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Linus Walleij authored
This reverts commit d0511b54. After some time it was noticed that the Tegra186 among others were experiencing problems when making this into a module. Signed-off-by:
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Gustavo A. R. Silva authored
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/da20103af0c22424c5d08a12f7107771bf4c01c5.1605896059.git.gustavoars@kernel.orgSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
Add pins, groups and functions for QSPIO[01]. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201119130926.25692-5-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Lad Prabhakar authored
Add pins, groups and functions for QSPIO[01]. Signed-off-by:
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Lad Prabhakar authored
Add pins, groups and functions for QSPIO[01]. Signed-off-by:
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Lad Prabhakar authored
Add pins, groups and functions for QSPIO[01]. Signed-off-by:
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- 17 Nov, 2020 2 commits
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Fabio Estevam authored
Since commit 4b563a06 ("ARM: imx: Remove imx21 support") the imx21 SoC is no longer supported. Get rid of its pinctrl driver too, which is now unused. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20201110190210.29376-1-festevam@gmail.comSigned-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.11 - Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H, - Image size optimizations and code consolidations, - Minor fixes and improvements.
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- 16 Nov, 2020 1 commit
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Andy Shevchenko authored
Baytrail pin control has a common register to set up debounce timeout. When a pin configuration requested debounce to be disabled, the rest of the pins may still want to have debounce enabled and thus rely on the common timeout value. Avoid clearing debounce value when turning it off for one pin while others may still use it. Fixes: 658b476c ("pinctrl: baytrail: Add debounce configuration") Depends-on: 04ff5a09 ("pinctrl: baytrail: Rectify debounce support") Depends-on: 827e1579 ("pinctrl: baytrail: Rectify debounce support (part 2)") Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com>
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- 13 Nov, 2020 9 commits
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Rikard Falkeborn authored
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the ops field in the regulator_desc struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.comSigned-off-by:
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Geert Uytterhoeven authored
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: -
Geert Uytterhoeven authored
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD) registers, like R-Car Gen3 and RZ/G2. Update the function to handle SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car Gen1/Gen2 and RZ/G1. Reduce code duplication by converting the R-Car M1A pin control driver to use the common handler. Note that this changes behavior in case the (invalid!) option "bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored silently; after this change, it is considered the same as "bias-pull-up". Signed-off-by:
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Geert Uytterhoeven authored
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car M1A uses register offsets instead of register physical addresses. This is different from the handling on other R-Car parts. Convert the bias handling from register offsets to physical addresses. This increases uniformity, and prepares for consolidation of the bias handling. Signed-off-by:
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Geert Uytterhoeven authored
All pin control drivers for R-Car Gen3 SoCs contain identical bias handling. Reduce code duplication by moving it to the common pinctrl.c code. Signed-off-by:
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Geert Uytterhoeven authored
Shrink sh_pfc_pin_config from 8 to 2 bytes: - The mux_set flag can be removed, as a non-zero mark value means the same (zero = PINMUX_RESERVED is an invalid mark value), - The gpio_enabled flag needs only a single bit, - Mark values are small integers, and can easily fit in a 15-bit bitfield. This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB. Signed-off-by: -
Geert Uytterhoeven authored
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is present in between the enum_id and name members of the sh_pfc_pin structure. Get rid of this hole by sorting the structure's members by decreasing size. This saves up to 1.5 KiB per enabled SoC, and reduces the size of a kernel including support for all R-Car Gen3 SoCs by more than 10 KiB. This has no size impact on SH and arm32. Signed-off-by:
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Geert Uytterhoeven authored
Fix a few singular vs. plural grammar issues in comments. Signed-off-by:
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Geert Uytterhoeven authored
Commit b13431ed ("pinctrl: sh-pfc: Remove incomplete flag "cfg->type"") removed the last statement in between the goto and the label. Hence remove both. Signed-off-by:
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