- 20 May, 2021 40 commits
-
-
Lang Yu authored
When amdgpu_ib_ring_tests failed, the reset logic called amdgpu_device_ip_suspend twice, then deadlock occurred. Deadlock log: [ 805.655192] amdgpu 0000:04:00.0: amdgpu: ib ring test failed (-110). [ 806.290952] [drm] free PSP TMR buffer [ 806.319406] ============================================ [ 806.320315] WARNING: possible recursive locking detected [ 806.321225] 5.11.0-custom #1 Tainted: G W OEL [ 806.322135] -------------------------------------------- [ 806.323043] cat/2593 is trying to acquire lock: [ 806.323825] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.325668] but task is already holding lock: [ 806.326664] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.328430] other info that might help us debug this: [ 806.329539] Possible unsafe locking scenario: [ 806.330549] CPU0 [ 806.330983] ---- [ 806.331416] lock(&adev->dm.dc_lock); [ 806.332086] lock(&adev->dm.dc_lock); [ 806.332738] *** DEADLOCK *** [ 806.333747] May be due to missing lock nesting notation [ 806.334899] 3 locks held by cat/2593: [ 806.335537] #0: ffff888100d3f1b8 (&attr->mutex){+.+.}-{3:3}, at: simple_attr_read+0x4e/0x110 [ 806.337009] #1: ffff888136b1fd78 (&adev->reset_sem){++++}-{3:3}, at: amdgpu_device_lock_adev+0x42/0x94 [amdgpu] [ 806.339018] #2: ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.340869] stack backtrace: [ 806.341621] CPU: 6 PID: 2593 Comm: cat Tainted: G W OEL 5.11.0-custom #1 [ 806.342921] Hardware name: AMD Celadon-CZN/Celadon-CZN, BIOS WLD0C23N_Weekly_20_12_2 12/23/2020 [ 806.344413] Call Trace: [ 806.344849] dump_stack+0x93/0xbd [ 806.345435] __lock_acquire.cold+0x18a/0x2cf [ 806.346179] lock_acquire+0xca/0x390 [ 806.346807] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.347813] __mutex_lock+0x9b/0x930 [ 806.348454] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.349434] ? amdgpu_device_indirect_rreg+0x58/0x70 [amdgpu] [ 806.350581] ? _raw_spin_unlock_irqrestore+0x47/0x50 [ 806.351437] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.352437] ? rcu_read_lock_sched_held+0x4f/0x80 [ 806.353252] ? rcu_read_lock_sched_held+0x4f/0x80 [ 806.354064] mutex_lock_nested+0x1b/0x20 [ 806.354747] ? mutex_lock_nested+0x1b/0x20 [ 806.355457] dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.356427] ? soc15_common_set_clockgating_state+0x17d/0x19 [amdgpu] [ 806.357736] amdgpu_device_ip_suspend_phase1+0x78/0xd0 [amdgpu] [ 806.360394] amdgpu_device_ip_suspend+0x21/0x70 [amdgpu] [ 806.362926] amdgpu_device_pre_asic_reset+0xb3/0x270 [amdgpu] [ 806.365560] amdgpu_device_gpu_recover.cold+0x679/0x8eb [amdgpu] Signed-off-by:Lang Yu <Lang.Yu@amd.com> Acked-by:
Christian KÃnig <christian.koenig@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Aaron Liu authored
Starting from Navi+, the rlc reference clock is used for system clock from vbios gfx_info table. It is incorrect to use core_refclk_10khz of vbios smu_info table as system clock. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
-
Guchun Chen authored
Current golden setting is out of date. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
-
Guchun Chen authored
Current golden setting is out of date. Signed-off-by:
-
xinhui pan authored
looks like we forget to set ttm->sg to NULL. Hit panic below [ 1235.844104] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7b4b: 0000 [#1] SMP DEBUG_PAGEALLOC NOPTI [ 1235.989074] Call Trace: [ 1235.991751] sg_free_table+0x17/0x20 [ 1235.995667] amdgpu_ttm_backend_unbind.cold+0x4d/0xf7 [amdgpu] [ 1236.002288] amdgpu_ttm_backend_destroy+0x29/0x130 [amdgpu] [ 1236.008464] ttm_tt_destroy+0x1e/0x30 [ttm] [ 1236.013066] ttm_bo_cleanup_memtype_use+0x51/0xa0 [ttm] [ 1236.018783] ttm_bo_release+0x262/0xa50 [ttm] [ 1236.023547] ttm_bo_put+0x82/0xd0 [ttm] [ 1236.027766] amdgpu_bo_unref+0x26/0x50 [amdgpu] [ 1236.032809] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7aa/0xd90 [amdgpu] [ 1236.040400] kfd_ioctl_alloc_memory_of_gpu+0xe2/0x330 [amdgpu] [ 1236.046912] kfd_ioctl+0x463/0x690 [amdgpu] Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
-
Alex Deucher authored
To stay consistent with the user's setting. v2: rebase on multi-eDP support Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
-
Alex Deucher authored
And cache the value. These can be used by the backlight callbacks and modesetting functions. v2: rebase on latest backlight changes. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337Reviewed-by:
-
Mukul Joshi authored
For Aldebaran, driver needs to query DramMegaBaseAddress to check if DF hashing is enabled. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Acked-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
-
James Zhu authored
Add video_codecs query support for aldebaran. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
-
Dennis Li authored
The function kfd_lookup_process_by_pasid will increase the reference count of kfd_process object, its caller should call kfd_unref_process to decrease the reference count. Otherwise resource leakage will happen. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Felix Kuehling authored
The dmabuf attachment should be updated by moving the SG BO to DOMAIN_CPU and back to DOMAIN_GTT. This does not necessarily invoke the populate/unpopulate callbacks. Do this in backend_bind/unbind instead. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Oak Zeng <Oak.Zeng@amd.com> Acked-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
-
Felix Kuehling authored
Use DMABufs with dynamic attachment to DMA-map GTT BOs on other GPUs. Signed-off-by:
-
Felix Kuehling authored
This is needed to avoid deadlocks with DMA buf import in the next patch. Also move PT/PD validation out of kfd_mem_attach, that way the caller can bo this unconditionally. Signed-off-by:
-
Felix Kuehling authored
DMA map kfd_mem_attachments in update_gpuvm_pte. This function is called with the BO and page tables reserved, so we can safely update the DMA mapping. DMA unmap when a BO is unmapped from a GPU and before updating mappings in restore workers. Signed-off-by:
-
Felix Kuehling authored
Add BO-type specific helpers functions to DMA-map and unmap kfd_mem_attachments. Implement this functionality for userptrs by creating one SG BO per GPU and filling it with a DMA mapping of the pages from the original mem->bo. Signed-off-by:
-
Felix Kuehling authored
Do AQL queue double-mapping with a single attach call. That will make it easier to create per-GPU BOs later, to be shared between the two BO VA mappings on the same GPU. Freeing the attachments is not necessary if map_to_gpu fails. These will be cleaned up when the kdg_mem object is destroyed in amdgpu_amdkfd_gpuvm_free_memory_of_gpu. Signed-off-by:
-
Felix Kuehling authored
For now they all reference the same BO. For correct DMA mappings they will refer to different BOs per-GPU. Signed-off-by:
-
Felix Kuehling authored
This name is more fitting, especially for the changes coming next to support multi-GPU systems with proper DMA mappings. Cleaned up the code and renamed some related functions and variables to improve readability. Signed-off-by:
-
Jingwen Chen authored
[Why] the gem object rfb->base.obj[0] is get according to num_planes in amdgpufb_create, but is not put according to num_planes [How] put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by:
-
YuBiao Wang authored
[Why] IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it. [How] Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov. Reviewed-by:
Chen, Horace <Horace.Chen@amd.com> Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Signed-off-by:
-
Joe Perches authored
/n should be \n Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] MALL requires idle optimizations to be enabled. This enables MALL feature on dcn303 Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] Add beige_goby_ta.bin to module firmware table and call psp init for TA Signed-off-by:
-
Joshua Aberback authored
[Why] This update was made for DCN30, but it is needed for DCN303 as well Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] Absense of this callback causes null pointer dereference. Add the corresponding callback in dcn303 resources. Fixes: 443dfba0 ("drm/amd/display: fix dcn3+ bw validation soc param update sequence") Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] Adds DCN IP block initialization for Beige Goby Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] Adds the firmware definition and missing cases statement hooks for Beige Goby support in AMDGPU DM. Signed-off-by:
-
Aurabindo Pillai authored
[How] * Add MIT license to all new files as SPDX tag. * Fix copyright year Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by:
Chris Park <Chris.Park@amd.com> Signed-off-by:
-
Aurabindo Pillai authored
[Why&How] Adds registers definitions required for Beige Goby initial support. Signed-off-by:
-
Jiansong Chen authored
beige_goby has similar gc_10_3 ip with sienna_cichlid, so follow its registers offset setting. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
-
Chengming Gui authored
Enable gfxoff in driver side based on SMC#73.3 v2: fix typo 'Eanble' --> 'Enable' Signed-off-by:
-
Chengming Gui authored
Switch from softPPTable to VBIOS PPTable. v2: drop extra parens (Alex) Signed-off-by:
-
Tao Zhou authored
Enable cgls to improve the runtime power efficiency. Signed-off-by:
-
Veerabadhran Gopalakrishnan authored
Enable VCN CG for BEIGE GOBY Signed-off-by:
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by:
-
Tao Zhou authored
Enable ih clock gating for beige_goby. Signed-off-by:
-
Tao Zhou authored
Enable hdp MGCG and LS for beige_goby. Signed-off-by:
-
Tao Zhou authored
Enable mc CG and LS for beige_goby. Signed-off-by:
-
Tao Zhou authored
Enable athub/mmhub power gating for beige_goby. Signed-off-by:
-
Tao Zhou authored
Enable athub cg for beige_goby. Signed-off-by:
-
