- 19 Nov, 2022 3 commits
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Ville Syrjälä authored
We call drm_encoder_init() before determining the correct encoder type, thus we always end up with DRM_MODE_ENCODER_NONE. Determine the correct encoder type earlier. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221118105525.27254-4-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
If we can't initialize the DVO encoder also free the connector state allocated by intel_connector_alloc(). Signed-off-by:
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Ville Syrjälä authored
intel_dvo.panel_wants_dither is only set but never used. We can't do dithering on the gmch side anyway since the dithering logic is part of the integrated LVDS port and not available for other output types. Signed-off-by:
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- 18 Nov, 2022 13 commits
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Matt Roper authored
DG2 has been very usable for a while now, and all of the uapi changes related to fundamental platform usage have been finalized. Recent CI results have also been healthy, so we're ready to drop the force_probe requirement and enable the platform by default. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Acked-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
MTL LPDDR5 reported 16b with 8 channels. Previous platforms reported 32b with 4 channels and hence needed a multiplication by a factor of 2. Skip increasing the channels for MTL. v2: Use version check instead of platform check(MattR) Bspec: 64631 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
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Radhakrishna Sripada authored
MEM_SS_INFO_GLOBAL Register info read from the hardware is cached in val. However the variable is being modified when determining the DRAM type thereby clearing out the channels and qgv info extracted later in the function xelpdp_get_dram_info. Preserve the register value and use extracted fields in the switch statement. Fixes: 825477e7 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox") Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Matt Atwood authored
Add stepping-substepping info in accordance to bpsec changes. Bspec: 55376 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by:
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Imre Deak authored
MTL+ requires the AUX_IO power for the main link only on eDP, so don't enable it in other cases. v2: - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
Factor out functions to get/put the AUX_IO power domain for the main link on DDI ports. While at it clarify the corresponding code comment. No functional change. v2: - s/(get/put)_aux_power_for_main_link/main_link_aux_power_domain_(get/put) (Jani) - Clarify in the code comment that AUX_IO is needed only by TypeC besides eDP/PSR. v3: - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr. v4: - Don't call fetch_and_zero() with side-effect during variable declaration. (Ville) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
Add the missing DC_OFF power domain -> DC_OFF power well mappings on all platforms. This didn't cause a problem as the DC_OFF power domain is only used on JSL, where the mapping was already correct. Signed-off-by:
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Imre Deak authored
BXT and GLK were missing the AUX_IO_A power domain -> PHY A common power well mapping, add these now. This didn't cause a problem as the AUX_IO_A and DDI_LANES_A power domains are acquired together. Signed-off-by:
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Imre Deak authored
Starting with TGL eDP is supported on ports B+ (besides port A), so make sure DC states are not blocked on any such ports. For this add an AUX_IO_<port> power domain for each port with eDP support. These domains similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an enabled port, whereas the existing AUX_<port> domains enable both the AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers. v2: (Ville) - Split the change using AUX vs. AUX_IO on port A to a separate patch. - Select AUX_IO vs. AUX based on crtc_state->has_psr instead of is_edp(). v3: - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr. v4: - Fix warn in intel_display_power_aux_io_domain(). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
Use the AUX_IO_A display power domain only for eDP on port A where PSR is also supported. This is the case where DC states need to be enabled while the output is enabled - ensured by AUX_IO_A domain not enabling the DC_OFF power well. Otherwise port A can be treated the same way as other ports with an external DP output: using the AUX_<port> domain which disables the unrequired DC states. This change prepares for the next patch enabling DC states on all ports supporting eDP/PSR besides port A. v2: - Check the encoder PSR capability instead of PSR being enabled in the crtc_state, as the latter can be changed with a fastset. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
Move the definition of the AUX_IO_A power domain, requiring only the corresponding AUX_IO_A power well to be enabled, before all the AUX_<port> power domains, which require both the AUX_IO_<port> and the DC_OFF power wells to be enabled. No functional change. Signed-off-by:
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Imre Deak authored
Since the current size of intel_display_power_domain_set struct is close to 1kB, it's better to use preallocated memory for it. The only user of the intel_display_power_get/put_in_set() allocating the struct on stack is hsw_get_pipe_config(), so we can avoid potential stack overallocations by moving the struct here to the preallocated intel_crtc struct (hsw_get_pipe_config() is non-reentrant wrt. each CRTC). This patch replaces https://lore.kernel.org/intel-gfx/20221107170917.3566758-5-imre.deak@intel.com/T/#md3f6cdf17fcdSuggested-by:
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Imre Deak authored
The intel_display_power_*_domain() functions should always warn if a default domain is returned as a fallback, fix this up. Spotted by Ville. Fixes: 979e1b32 ("drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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- 17 Nov, 2022 24 commits
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Ville Syrjälä authored
Fix up some function argument alignment fails. Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> Cc: Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Ville Syrjälä authored
Make the two branches of get_saved_enc() look alike. Currently they look different even though they do exactly the same thing apart from == vs. != for the MST comparison. Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> Cc: Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Ville Syrjälä authored
When doing HDMI+non-HDMI cloning the other sink can't get the infoframes/etc. so stuff like limited range output is not a good idea. Similarly when doing HDMI+HDMI cloning on g4x (only platform where we allow it) only one of the ports can receive infoframes and so again using any fancy stuff is a bad idea. We also don't track the inforames/audio state per-port so we'd end up with some kind of random mismash state when multipled encoders try to compute the same stuff. And the hardware will in fact automagically disable audio/infoframe transmission if you try to enable it for multiple HDMI ports at the same time. Thus disable all HDMI specific features when cloning. Signed-off-by:
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Ville Syrjälä authored
YCbCr output requires infoframes and whatnot, so don't allow it when dealing with a DVI sink (or a HDMI sink we wish to treat as DVI). Signed-off-by:
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Ville Syrjälä authored
Start pulling some of the more platform specific things out from intel_hdmi_compute_config(). has_pch_encoder is clearly one such thing. Signed-off-by:
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Ville Syrjälä authored
Satisfy my ocd and define ilk_lut_12p4_ldw() before ilk_lut_12p4_udw(). That is the order all the other similar functions use. Reviewed-by:
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Ville Syrjälä authored
Add the missing ldw vs. udw information to the CGM (de)gamma bit definitions to make it a bit easier to see which should be used where. Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by:
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Ville Syrjälä authored
Use consistent bit definitions for the 12.4bit precision palette bits. We just define these alongside the ilk/snb register definitions and point to those from the icl+ superfine segment defines (and we also already pointed to them from the ivb+ precision palette defines). Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by:
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Ville Syrjälä authored
Use consistent bit definitions for the 10bit precision palette bits. We just define these alongside the ilk/snb register definitions and point to those from the ivb+ defines. Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by:
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Ville Syrjälä authored
Use consistent bit definitions for the legacy gamma LUT. We just define these alongside the pre-ilk register definitions and point to those from the ilk+ defines. Also use the these appropriately in the LUT entry pack/unpack functions. Reviewed-by:
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Ville Syrjälä authored
Include dev_name() in the tracpoints so one can filter based on the device. Example: echo 'dev=="0000:00:02.0"' > events/i915/intel_cpu_fifo_underrun/filter v2: Reduce the magic macros, rebase Signed-off-by:
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Ville Syrjälä authored
Pass the device to the frontbuffer tracpoints. Will be used later to include the device name in the tracpoints. Signed-off-by:
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Ville Syrjälä authored
Print the name of the plane in the fbc tracepoints. As the pipe<->plane assignment can vary on old hw it's probably more helpful to see both the plane and the pipe names together. Signed-off-by:
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Ville Syrjälä authored
Pass intel_plane rather than drm_plane to the plane tracepoints. Matches what we do eg. with the fbc tracepoints. Using the same type for everything will help with digging out the device name from the plane in the future. Signed-off-by:
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Jani Nikula authored
Move display suspend/resume and display reset modeset state and ctx members under drm_i915_private display sub-struct. Signed-off-by:
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Jani Nikula authored
Move display global state member under drm_i915_private display sub-struct. Prefer adding anonymous sub-structs even for single members that aren't our own structs. Remove a nearby stale comment while at it. Signed-off-by:
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Jani Nikula authored
Move display hti/hdport related members under drm_i915_private display sub-struct. Prefer adding anonymous sub-structs even for single members that aren't our own structs. Signed-off-by:
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Jani Nikula authored
The HTI or HDPORT handling is sprinkled around. Centralize to one place. Add a note about how subtle the mapping from HDPORT_STATE register to dpll mask actually is. Signed-off-by:
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https://github.com/intel/gvt-linuxRodrigo Vivi authored
gvt-next-2022-11-17 - kernel doc fixes - remove vgpu->released sanity check - small clean up Signed-off-by:
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Jani Nikula authored
Panel power off delay is the time the panel power needs to remain off after being switched off, before it can be switched on again. For the purpose of respecting panel power off delay at driver probe, assuming the panel was last switched off at driver probe is overly pessimistic. If the panel was never on, we'd end up waiting for no reason. We don't know what has happened before kernel boot, but we can make some assumptions: - The panel may have been switched off right before kernel boot by some pre-os environment. - After kernel boot, the panel may only be switched off by i915. - At i915 driver probe, only a previously loaded and removed i915 may have switched the panel power off. With these assumptions, we can initialize the last power off time to kernel boot time, if we also ensure i915 driver remove waits for the panel power off delay after switching panel power off. This shaves off the time it takes from kernel boot to i915 probe from the first panel enable, if (and only if) the panel was not already enabled at boot. The encoder destroy hook is pretty much the last place where we can wait, right after we've ensured the panel power has been switched off, and before the whole encoder is destroyed. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7417 Cc: Lee Shawn C <shawn.c.lee@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Lee Shawn C <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221116150657.1347504-1-jani.nikula@intel.com
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Jiapeng Chong authored
The function get_pt_type is defined in the gtt.c file, but not called elsewhere, so delete this unused function. drivers/gpu/drm/i915/gvt/gtt.c:285:19: warning: unused function 'get_pt_type'. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2277Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20220926064044.53016-1-jiapeng.chong@linux.alibaba.comReviewed-by:
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wangjianli authored
Delete the redundant word 'the'. Signed-off-by:
wangjianli <wangjianli@cdjrlc.com> Signed-off-by:
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Zhi Wang authored
The life cycle of a vGPU, which is represented by a vfio_device, has been managed by the VFIO core logic. Remove the vgpu->released, which was used for a sanity check on the removal path of the vGPU instance. The sanity check has already been covered in the VFIO core logic. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Cc: Jason Gunthorpe <jgg@nvidia.com> Cc: intel-gvt-dev@lists.freedesktop.org Suggested-by:
Alex Williamson <alex.williamson@redhat.com> Signed-off-by:
Zhi Wang <zhi.a.wang@intel.com> Signed-off-by:
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Paulo Miguel Almeida authored
struct gvt_firmware_header has a crc32 member in which all members that come after the that field are used to calculate it. The previous implementation added the value '4' (crc32's u32 size) to calculate the crc32_start offset which came across as a bit cryptic until you take a deeper look at the struct. This patch changes crc32_start offset to the 'version' member which is the first member of the struct gvt_firmware_header after crc32. It's worth mentioning that doing a build before/after this patch results in no binary output differences. Signed-off-by:
Paulo Miguel Almeida <paulo.miguel.almeida.rodenas@gmail.com> Signed-off-by:
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