- 14 Dec, 2016 1 commit
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Petr Mladek authored
The memory barrier is not enough to protect queuing works into a destroyed cq kthread. Just imagine the following situation: CPU1 CPU2 rvt_cq_enter() worker = cq->rdi->worker; rvt_cq_exit() rdi->worker = NULL; smp_wmb(); kthread_flush_worker(worker); kthread_stop(worker->task); kfree(worker); // nothing queued yet => // nothing flushed and // happily stopped and freed if (likely(worker)) { // true => read before CPU2 acted cq->notify = RVT_CQ_NONE; cq->triggered++; kthread_queue_work(worker, &cq->comptask); BANG: worker has been flushed/stopped/freed in the meantime. This patch solves this by protecting the critical sections by rdi->n_cqs_lock. It seems that this lock is not much contended and looks reasonable for this purpose. One catch is that rvt_cq_enter() might be called from IRQ context. Therefore we must always take the lock with IRQs disabled to avoid a possible deadlock. Signed-off-by:Petr Mladek <pmladek@suse.com> Signed-off-by:
Doug Ledford <dledford@redhat.com>
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- 11 Dec, 2016 25 commits
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Bart Van Assche authored
Defining static data structures in a header file is wrong because this causes the data structure to be instantiated once in every .c file it is included in. Hence move the definition of a static array from a header file into the only .c file in which it is used. Signed-off-by:
Bart Van Assche <bart.vanassche@sandisk.com> Cc: Dennis Dalessandro <dennis.dalessandro@intel.com> Cc: Dean Luick <dean.luick@intel.com> Signed-off-by:
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Bhumika Goyal authored
Declare the structure mmu_notifier_ops as const as it is only stored in the ops field of a mmu_notifier structure. The ops field is of type const struct mmu_notifier_ops *, so mmu_notifier_ops structures having this property can be declared as const. Done using coccinelle: @r1 disable optional_qualifier @ identifier i; position p; @@ static struct mmu_notifier_ops i@p = {...}; @ok1@ identifier r1.i; position p; struct mmu_rb_handler handler; @@ handler.mn.ops=&i@p @bad@ position p!={r1.p,ok1.p}; identifier r1.i; @@ i@p @depends on !bad disable optional_qualifier@ identifier r1.i; @@ static +const struct mmu_notifier_ops i={...}; @depends on !bad disable optional_qualifier@ identifier r1.i; @@ +const struct mmu_notifier_ops i; File size before: text data bss dec hex filename 3566 72 16 3654 e46 drivers/infiniband/hw/hfi1/mmu_rb.o File size after: text data bss dec hex filename 3658 0 16 3674 e5a drivers/infiniband/hw/hfi1/mmu_rb.o Signed-off-by:Bhumika Goyal <bhumirks@gmail.com> Reviewed-by:
Ira Weiny <ira.weiny@intel.com> Signed-off-by:
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Mike Marciniszyn authored
Add rvt_div_round_up_mtu() and rvt_div_mtu() routines to do the computation based on the pmtu and the log_pmtu. Change divides in qib, hfi1 to use the new inlines. Reviewed-by:
Kaike Wan <kaike.wan@intel.com> Signed-off-by:
Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by:
Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by:
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Mike Marciniszyn authored
Convert to use new swqe put routine. Reviewed-by:
Brian Welty <brian.welty@intel.com> Signed-off-by:
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Mike Marciniszyn authored
Add a helper to release mr references held by an swqe. Reviewed-by:
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Harish Chegondi authored
Do not allocate credit return base and DMA memory for NUMA nodes without CPUs. Reviewed-by:
Harish Chegondi <harish.chegondi@intel.com> Signed-off-by:
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Mike Marciniszyn authored
Convert cq completion returns in both rdmavt drivers to use the new helper. Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
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Mike Marciniszyn authored
This is for use by client drivers to drive send completions into a CQ. A new exported table allows for the mapping of ib_wr_opcode into a ib_wc_opcode. Reviewed-by:
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Sebastian Sanchez authored
Use the standard driver wrapper for QP reference counters. This makes the code more maintainable. Fixes: Commit 4d6f85c3 ("IB/rdmavt, IB/qib, IB/hfi1: Use new QP put get routines") Reviewed-by:
Sebastian Sanchez <sebastian.sanchez@intel.com> Signed-off-by:
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Sebastian Sanchez authored
Some parts of the code don't use the standard driver wrapper for memory region reference counters. Use the standard driver wrapper throughout the code. Reviewed-by:
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Sebastian Sanchez authored
Some parts of the code don't use the standard release wrapper rvt_put_qp() for decrementing and testing the refcount to then try to use a resource. Replace this code with the standard driver wrapper. Fixes: Commit 4d6f85c3 ("IB/rdmavt, IB/qib, IB/hfi1: Use new QP put get routines") Reviewed-by:
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Dean Luick authored
The driver should not change the external device request completed bit when not actually doing an external device request. Reviewed-by:
Easwar Hariharan <easwar.hariharan@intel.com> Signed-off-by:
Dean Luick <dean.luick@intel.com> Signed-off-by:
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Sebastian Sanchez authored
In sc_buffer_alloc(), the sc->alloc_lock is released before calling sc_release_update(), and it is reacquired after the function call. This causes CPU lock trading. Fix it by not dropping the lock before calling sc_release_update(). Reviewed-by:
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Mitko Haralanov authored
The s_cur_sge field in the qp structure holds a pointer to the SGE of the currently processed WQE. It assumes the protection of the RVT_S_BUSY flag to prevent the changing of this field while the send engine is using it. This scheme works as long as there is only one instance of the send engine running at a time. Scaling of the send engine to multiple cores would break this assumption as there could be multiple instances of the send engine running on different CPUs. This opens a window where the QP's RVT_S_BUSY flag is not set but the send engine is still running. To prevent accidental changing of the s_cur_sge pointer, the QP's dependence on it is removed. The SGE pointer is now stored in the verbs_txreq, which is a per-packet data structure. This ensures that each individual packet has it's own pointer, which is setup while the RVT_S_BUSY flag is set. Reviewed-by:
Mitko Haralanov <mitko.haralanov@intel.com> Signed-off-by:
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Mike Marciniszyn authored
Add tracing of MR segment information. Reviewed-by:
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Dean Luick authored
Low power QSFP AOC cables require a different SerDes Tx PLL bandwidth setting than the default. The 8051 firmware does not know the details, so the driver needs to tell the firmware through a special setting. Reviewed-by:
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Tadeusz Struk authored
The struct hfi1_affinity is not used anymore. We use the struct hfi1_affinity_node and hfi1_affinity_node_list instead. Reviewed-by:
Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by:
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Don Hiatt authored
The qp->s_cur_size field assumes that the S_BUSY bit protects the field from modification after the slock is dropped. Scaling the send engine to multiple cores would break that assumption. Correct the issue by carrying the payload size in the txreq structure. Reviewed-by:
Don Hiatt <don.hiatt@intel.com> Signed-off-by:
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Jianxin Xiong authored
Previously tools like hfi1stats had to access these counters through debugfs, which often caused permission issue for non-root users. It is not always acceptable to change the debugfs mounting permission due to security concerns. When exposed under the IB stats interface, the counters are universally readable by default. Reviewed-by:
Jianxin Xiong <jianxin.xiong@intel.com> Signed-off-by:
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Dennis Dalessandro authored
Split rdmavt traces into separate files to preserve the original hierarchy since only one trace sub system may now be defined per header file. Reviewed-by:
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Jakub Pawlak authored
For the received packets with payload less or equal 8DWS RxDmaDataFifoRdUncErr is not reported. There is set RHF.EccErr if the header is not suppressed. When such packet is detected on the send side the header suppression mechanism is disabled by clearing SH bit in the packet header. Reviewed-by:
Jakub Pawlak <jakub.pawlak@intel.com> Signed-off-by:
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Dean Luick authored
Both the 8051 memory and LCB register access require multiple steps and coordination with the driver. This cannot be safely done with resource0 alone. The 8051 memory is exported read-only. LCB is exported read/write. Reviewed-by:
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Sebastian Sanchez authored
qp->r_aflags is already protected by qp->r_lock, therefore, test_and_clear_bit() doesn't need to be atomic. Profile shows this function call is costly. Change the test_and_clear_bit() call to use the non-atomic variant. Reviewed-by:
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Dean Luick authored
When reading multiple dc8051 data memory locations at once, the read enabled field must be toggled at every address change. Do that by writing only the address first, then writing the enable. Reviewed-by:
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Dean Luick authored
Add the ability to read the new EPROM format. Reviewed-by:
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- 15 Nov, 2016 10 commits
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Sebastian Sanchez authored
Both pio_buf and send_context structs have oversized fields and have cachelines that can be optimized. Reduce oversized fields for both structs. Make sure pio_buf struct fits within a cacheline. Move read-only fields to their own cacheline in send_context struct. All of this will avoid cacheline trading as the ring progresses and pio buffers/send contexts are used. Reviewed-by:
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Sebastian Sanchez authored
The div instruction shows costly in profiles. Reviewed-by:
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Easwar Hariharan authored
Use scratch registers within the HFI1 device to recover signal integrity information that is then used to tune the channel. While there, update error messages to better convey the result of falling back to a backup file. Reviewed-by:
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Sebastian Sanchez authored
Profiling shows hot path struct members that need to be in a minimum set of cachelines. Group these struct member in the same cacheline: sc2vl_lock sc2vl rhf_rcv_function_map rcv_limit rhf_offset Group these struct member in the same cacheline: process_pio_send process_dma_send pport rcd int_counter flags num_pports first_user_ctxt Fill holes in struct hfi1_devdata revealed by pahole. Reviewed-by:
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Jakub Pawlak authored
This patch consolidates the node GUIDs and the port GUID handling and unifies access to these items. The knowledge of hfi1 GUIDs' design and their location are kept in accessors to centralize access. Reviewed-by:
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Mike Marciniszyn authored
Move buffers_allocated pcpu pointer to allocator line. Move hw_free pointer to releaser line. Fill other holes revealed by pahole. Reviewed-by:
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Mike Marciniszyn authored
Save a cacheline by having hot path calldowns together. Reviewed-by:
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Mike Marciniszyn authored
Profiling shows that the key validation is susceptible to cache line trading when accessing the lkey table. Fix by separating out the read mostly fields from the write fields. In addition the shift amount, which is function of the lkey table size, is precomputed and stored with the table pointer. Since both the shift and table pointer are in the same read mostly cacheline, this saves a cache line in this hot path. Reviewed-by:
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Mike Marciniszyn authored
Short circuit sdma_txclean() by adding an __sdma_txclean() that is only called when the tx has sdma mappings. Convert internal calls to __sdma_txclean(). This removes a call from the critical path. Reviewed-by:
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Mike Marciniszyn authored
Profiling suggests that the read_seqbegin() in the txreq put logic is colliding with other uses of the iowait lock. The packet at a time use of this lock dictates a unique lock to avoid reader/writer collisions when the number of vTxWait events is low. In order to support a unique lock the iowait struct embedded in the QP is extended to remember the lock that protects the queue head. The QP destroy removes that QP from any wait list. It doesn't need to know the head because of the linked list API, but it does need to know the lock required to protect the head. This also opens up the wait logic to have unique per resources locks which needs to be in future refinement. Reviewed-by:
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- 29 Oct, 2016 4 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 bugfix from Thomas Gleixner: "A single bugfix for the recent changes related to registering the boot cpu when this has not happened before prefill_possible_map(). The main problem with this change got fixed already, but we missed the case where the local APIC is not yet mapped, when prefill_possible_map() is invoked, so the registration of the boot cpu which has the APIC bit set in CPUID will explode. I should have seen that issue earlier, but all I can do now is feeling embarassed" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/smpboot: Init apic mapping before usage
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git://git.infradead.org/linux-ubifsLinus Torvalds authored
Pull ubi/ubifs fixes from Richard Weinberger: "This contains fixes for issues in both UBI and UBIFS: - A regression wrt overlayfs, introduced in -rc2. - An UBI issue, found by Dan Carpenter's static checker" * tag 'upstream-4.9-rc3' of git://git.infradead.org/linux-ubifs: ubifs: Fix regression in ubifs_readdir() ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds authored
Pull ARM SoC fixes from Olof Johansson: "We haven't seen a whole lot of fixes for the first two weeks since the merge window, but here is the batch that we have at the moment. Nothing sticks out as particularly bad or scary, it's mostly a handful of smaller fixes to several platforms. The Uniphier reset controller changes could probably have been delayed to 4.10, but they're not scary and just plumbing up driver changes that went in during the merge window. We're also adding another maintainer to Marvell Berlin platforms, to help out when Sebastian is too busy. Yay teamwork!" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: imx: mach-imx6q: Fix the PHY ID mask for AR8031 ARM: dts: vf610: fix IRQ flag of global timer ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path ARM: imx: gpc: Initialize all power domains arm64: dts: Updated NAND DT properties for NS2 SVK arm64: dts: uniphier: change MIO node to SD control node ARM: dts: uniphier: change MIO node to SD control node reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER arm64: dts: Add timer erratum property for LS2080A and LS1043A arm64: dts: rockchip: remove the abuse of keep-power-in-suspend ARM: multi_v7_defconfig: Enable Intel e1000e driver MAINTAINERS: add myself as Marvell berlin SoC maintainer bus: qcom-ebi2: depend on ARCH_QCOM or COMPILE_TEST ARM: dts: fix the SD card on the Snowball arm64: dts: rockchip: remove always-on and boot-on from vcc_sd arm64: dts: marvell: fix clocksource for CP110 master SPI0 ARM: mvebu: Select corediv clk for all mvebu v7 SoC
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