- 07 Jan, 2014 3 commits
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Chris Wilson authored
The bug from gen6_ppgtt_insert_entries() was replicated into gen8_ppgtt_insert_entries(). This applies the fix for the OOPS from the previous patch to the gen8 routine. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Chris Wilson authored
[ 89.237347] BUG: unable to handle kernel paging request at ffff880096326000 [ 89.237369] IP: [<ffffffff81347227>] gen6_ppgtt_insert_entries+0x117/0x170 [ 89.237382] PGD 2272067 PUD 25df0e067 PMD 25de5c067 PTE 8000000096326060 [ 89.237394] Oops: 0000 [#1] SMP DEBUG_PAGEALLOC [ 89.237404] CPU: 1 PID: 1981 Comm: gem_concurrent_ Not tainted 3.13.0-rc4+ #639 [ 89.237411] Hardware name: Intel Corporation 2012 Client Platform/Emerald Lake 2, BIOS ACRVMBY1.86C.0078.P00.1201161002 01/16/2012 [ 89.237420] task: ffff88024c038030 ti: ffff88024b130000 task.ti: ffff88024b130000 [ 89.237425] RIP: 0010:[<ffffffff81347227>] [<ffffffff81347227>] gen6_ppgtt_insert_entries+0x117/0x170 [ 89.237435] RSP: 0018:ffff88024b131ae0 EFLAGS: 00010286 [ 89.237440] RAX: ffff880096325000 RBX: 0000000000000400 RCX: 0000000000001000 [ 89.237445] RDX: 0000000000000200 RSI: 0000000000000001 RDI: 0000000000000010 [ 89.237451] RBP: ffff88024b131b30 R08: ffff88024cc3aef0 R09: 0000000000000000 [ 89.237456] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88024cc3ae00 [ 89.237462] R13: ffff88024a578000 R14: 0000000000000001 R15: ffff88024a578ffc [ 89.237469] FS: 00007ff5475d8900(0000) GS:ffff88025d020000(0000) knlGS:0000000000000000 [ 89.237475] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 89.237480] CR2: ffff880096326000 CR3: 000000024d531000 CR4: 00000000001407e0 [ 89.237485] Stack: [ 89.237488] ffff880000000000 0000020000000000 ffff88024b23f2c0 0000000100000000 [ 89.237499] 0000000000000001 000000000007ffff ffff8801e7bf5ac0 ffff8801e7bf5ac0 [ 89.237510] ffff88024cc3ae00 ffff880248a2ee40 ffff88024b131b58 ffffffff813455ed [ 89.237521] Call Trace: [ 89.237528] [<ffffffff813455ed>] ppgtt_bind_vma+0x3d/0x60 [ 89.237534] [<ffffffff8133d8dc>] i915_gem_object_pin+0x55c/0x6a0 [ 89.237541] [<ffffffff8134275b>] i915_gem_execbuffer_reserve_vma.isra.14+0x5b/0x110 [ 89.237548] [<ffffffff81342a88>] i915_gem_execbuffer_reserve+0x278/0x2c0 [ 89.237555] [<ffffffff81343d29>] i915_gem_do_execbuffer.isra.22+0x699/0x1250 [ 89.237562] [<ffffffff81344d91>] ? i915_gem_execbuffer2+0x51/0x290 [ 89.237569] [<ffffffff81344de6>] i915_gem_execbuffer2+0xa6/0x290 [ 89.237575] [<ffffffff813014f2>] drm_ioctl+0x4d2/0x610 [ 89.237582] [<ffffffff81080bf1>] ? cpuacct_account_field+0xa1/0xc0 [ 89.237588] [<ffffffff81080b55>] ? cpuacct_account_field+0x5/0xc0 [ 89.237597] [<ffffffff811371c0>] do_vfs_ioctl+0x300/0x520 [ 89.237603] [<ffffffff810757a1>] ? vtime_account_user+0x91/0xa0 [ 89.237610] [<ffffffff810e40eb>] ? context_tracking_user_exit+0x9b/0xe0 [ 89.237617] [<ffffffff81083d7d>] ? trace_hardirqs_on+0xd/0x10 [ 89.237623] [<ffffffff81137425>] SyS_ioctl+0x45/0x80 [ 89.237630] [<ffffffff815afffa>] tracesys+0xd4/0xd9 [ 89.237634] Code: 5b 41 5c 41 5d 41 5e 41 5f 5d c3 66 0f 1f 84 00 00 00 00 00 83 45 bc 01 49 8b 84 24 78 01 00 00 65 ff 0c 25 e0 b8 00 00 8b 55 bc <4c> 8b 2c d0 65 ff 04 25 e0 b8 00 00 49 8b 45 00 48 c1 e8 2d 48 [ 89.237741] RIP [<ffffffff81347227>] gen6_ppgtt_insert_entries+0x117/0x170 [ 89.237749] RSP <ffff88024b131ae0> [ 89.237753] CR2: ffff880096326000 [ 89.237758] ---[ end trace 27416ba8b18d496c ]--- This bug dates back to the original introduction of the gen6_ppgtt_insert_entries() Signed-off-by:
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Chris Wilson authored
The iommu and gfx on Ironlake do not like each other and require a big hammer to prevent hard machine hangs. In commit 5c042287 Author: Ben Widawsky <ben@bwidawsk.net> Date: Mon Oct 17 15:51:55 2011 -0700 drm/i915: ILK + VT-d workaround we added the workaround, but never emitted any debug message that it was active. Doing so should help identify known performance regressions. Signed-off-by:
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- 06 Jan, 2014 1 commit
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Tetsuo Handa authored
Since get_pid_task() grabs a reference on the task_struct, we have to drop the refcount after reading that task's comm name. Use pid_task() with RCU instead. Also, avoid directly reading like pid_task()->comm because pid_task() will return NULL if the task have already exit()ed. This patch fixes both problems. Signed-off-by:
Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Signed-off-by:
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- 18 Dec, 2013 1 commit
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Daniel Vetter authored
But only when we indeed set up a gtt mapping. We need this since the vma also holds a pages_pin_count, on top of the unconditional pages_pin_count we grab for all stolen objects (to avoid swap-out). This should avoid a pages_pin_count underrun when cleaning up framebuffers objects taken over from the BIOS. Chris mentioned in his review that this bug even predates the vma conversion. Reported-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by:
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- 17 Dec, 2013 24 commits
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Imre Deak authored
We use this hook starting from ILK onwards, so change the prefix accordingly. Also rename functions/struct names used from haswell_update_wm that are relevant to ILK already. No functional change. Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Imre Deak authored
Signed-off-by:
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Imre Deak authored
No functional change. Signed-off-by:
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Ville Syrjälä authored
Apparently always enabling the sprite scaler magically made sprites work on ILK in the past. I think the real reason for the failure was missing sprite watermark programming, and enabling the scaler effectively disabled LP1+ watermarks, which was enough to keep things going. Or it might be that the hardware more or less ignores watermarks for scaled sprites since things seem to work even if I leave sprite watermarks at 0 and disable all other planes except the sprite. In any case, we left the scaler always on but then failed to check whether we might be exceeding the scaler's source size limits. That caused the sprite to fail when a sufficiently large unscaled image was being displayed. Now that we're getting proper watermark programming for ILK, we can keep the scaler disabled unless we need to do actual scaling. This reverts commit 8aaa81a1. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Ville Syrjälä authored
As the watermark registers aren't double bufferd, clearing the watermarks immediately after writing the sprite registers can be hazardous. Until we have something better, add a wait for vblank between the two steps to make sure the sprite no longer needs the watermark levels before we clear them. Signed-off-by:
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Ville Syrjälä authored
When color keying is used, the primary may not be invisible even though the sprite fully covers it. So check for color keying before deciding to disable the primary plane. Signed-off-by:
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Ville Syrjälä authored
We now have a very clear method of disabling LP1+ wartermarks, and we can actually detect if we actually did disable them, or if they were already disabled. Use that to clean up the WaCxSRDisabledForSpriteScaling:ivb handling. I was hoping to apply the workaround in a way that wouldn't require a blocking wait, but sadly IVB really does appear to require LP1+ watermarks to be off for an entire frame before enabling sprite scaling. Simply disabling LP1+ watermarks during the previous frame is not enough, no matter how early in the frame we do it :( Signed-off-by:
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Ville Syrjälä authored
The new HSW watermark code can now handle ILK/SNB/IVB as well, so switch them over. Kill the old code. Signed-off-by:
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Ville Syrjälä authored
ILK doesn't like if we just write the LP1+ watermarks registers with 0. We need to just disable the watermarks by clearing the enable bit. Use that method also when disabling LP1+ watermarks in init_clock_gating. It looks like disabling the sprite LP1 watermarks can cause underruns even if we just toggle the WM1S_LP_EN bit. So treat that bit like the actual watermark numbers and avoid setting it to 0 immediately. Signed-off-by:
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Ville Syrjälä authored
Linetime watermarks don't exist on ILK/SNB/IVB, so don't compute them except on HSW. Signed-off-by:
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Ville Syrjälä authored
ILK has a bunch of issues with FBC. First of all, BSpec tells us that FBC WM should never be enabled. Secondly when FBC is enabled with FBC WM disabled, LP2+ watermarks must be disabled. Signed-off-by:
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Ville Syrjälä authored
Multi-pipe LP1+ watermarks are a HSW+ feature, so let's not do it on earlier generations. Signed-off-by:
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Ville Syrjälä authored
On ILK disabling LP1+ watermarks must be done carefully to avoid underruns. If we just write 0 to the register in the middle of the scan cycle we often get an underrun. So instead we have to leave the actual watermark levels in the register intact, and just toggle the enable bit. Presumably the hardware takes a while to get out of low power mode, and so the watermark level need to stay valid until that time. We also have to be careful with the WM1S_LP_EN bit. It seems the hardware more or less treats it like the actual watermarks numbers, and so we must not toggle it too soon. Just leave it alone when disabling the LP1+ watermarks. Signed-off-by:
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Ville Syrjälä authored
ILK/SNB don't have LP2+ watermarks for sprites. Also the LP1 sprite watermark register has its own enable bit. Take these differences into account when programming the LP1+ registers. Signed-off-by:
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Ville Syrjälä authored
On ILK/SNB only LP0/1 watermarks can be enabled when sprites are enabled, and on ILK/SNB/IVB sprite scaling is limited to LP0 only. So we can avoid computing the extra levels we're never going to use. Signed-off-by:
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Ville Syrjälä authored
Add a new function ilk_wm_lp_latency() which will tell us what to write into the WM_LPx register latency field. HSW is different from erlier gens in this regard. Signed-off-by:
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Ville Syrjälä authored
On IVB the display data buffer partitioning control lives in the DISP_ARB_CTL2 register. Add the relevant defines/code for it. Signed-off-by:
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Daniel Vetter authored
Otherwise we don't kick out firmware framebuffers like vesafb and efifb when CONFIG_DRM_I915_FBDEV=n but CONFIG_FB=y. There's still the pesky issue with vgacon which we should somehow replace with the dummy console at least. We have a similar issue at module un/reload, since vgacon state is terminally botched after i915.ko has loaded in modeset mode. But this gets us a step further at least. v2: Use IS_ENABLED - I always get this wrong for tristates. Spotted by Jani. Reported-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Damien Lespiau authored
Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Daniel Vetter authored
Noticed while reviewing a patch and couldn't resist the OCD. Reviewed-by:
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Ben Widawsky authored
Aside from the fact that it leaves confusing dumps on error capture, it is entirely unnecessary, and potentially harmful in cases like BDW, where the instruction has changed. In reality (seemingly), this will have no behavioral impact. Signed-off-by:
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Ben Widawsky authored
A few command were out of numerical order and had different spacing. Put them back in numerical order, with proper spacing. Signed-off-by:
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Jesse Barnes authored
We only need to init the reg offset for DPIO once, but we need to reset DPIO at resume time and at init time. Signed-off-by:
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Jesse Barnes authored
Just add an early init since we may need to access DPIO regs early on. The init call in modeset_init_hw is also needed for the resume case, when we need to reset DPIO to keep things happy. v2: split reset and reg init v3: split patches (Daniel) Signed-off-by:
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- 16 Dec, 2013 3 commits
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Jani Nikula authored
The whole file is wrapped around in #if defined(CONFIG_DEBUG_FS) anyway, so skip the file at the build level already. Signed-off-by:
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Wei Yongjun authored
In case of error, the function debugfs_create_file() returns NULL pointer not ERR_PTR() if debugfs is enabled. The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by:
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Jani Nikula authored
We don't actually do anything with the information yet, but parse and log what's in the VBT. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by:
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- 14 Dec, 2013 3 commits
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Paulo Zanoni authored
Now that all the infrastructure is in place and all the tests from pm_pc8 pass, we can finally enable the feature. Signed-off-by:
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Paulo Zanoni authored
So we'll get a fault when someone tries to access the mmap, then we'll wake up from D3. v2: - Rebase v3: - Use gtt active/inactive Testcase: igt/pm_pc8/gem-mmap-gtt Signed-off-by:
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Paulo Zanoni authored
The hangcheck function requires the hardware to be working, and if we're suspending we're going to put the HW in D3 state. Signed-off-by:
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- 13 Dec, 2013 4 commits
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Ben Widawsky authored
WaVSRefCountFullforceMissDisable and WaDSRefCountFullforceMissDisable VS is a carry-over from HSW, and DS is likely not used by anyone yet. Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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Ben Widawsky authored
I stumbled on to some unimplemented errata. To be honest, I am not really sure of the impact, just that the docs say to do. No w/a name for this one. v2: v1 was a stale thing which should have never seen the light of day. (Haihao) Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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Ville Syrjälä authored
Not all registers need forcewake even if they're not shadowed. Add the missing check to gen8_writeX() to avoid needless forcewake usage when writing eg. display registers. v2: Use straight up <0x40000 check instead of NEEDS_FORCE_WAKE() Reviewed-by:
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Ville Syrjälä authored
The BIOS or someone else might have done something bad and there might be old GT FIFO erros reported in GTFIFODBG. Clear those out in intel_uncore_early_sanitize() to make sure we don't mistake them for our problems. Signed-off-by:
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- 12 Dec, 2013 1 commit
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Mika Kuoppala authored
If test is running, irq_get was not called so we should gain balance by not doing irq_put "So the rule is: if you access unlocked values, you use ACCESS_ONCE(). You don't say "but it can't matter". Because you simply don't know." -- Linus v2: use local variable so it can't change during test (Chris) v3: update commit msg and use ACCESS_ONCE (Ville) Signed-off-by:
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