- 01 Feb, 2023 2 commits
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Zeng Heng authored
This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Signed-off-by:
Zeng Heng <zengheng4@huawei.com> Link: https://lore.kernel.org/r/20220928151346.1942977-1-zengheng4@huawei.comSigned-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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AngeloGioacchino Del Regno authored
This driver does exactly devm_clk_get() and clk_prepare_enable() right after, which is exactly what devm_clk_get_enabled() does: clean that up by switching to the latter. This commit brings no functional changes. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221006110935.59695-1-angelogioacchino.delregno@collabora.comSigned-off-by:
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- 31 Jan, 2023 9 commits
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Roger Lu authored
The o_slope value is dependent of the o_slope_sign, refactor code to get rid of unnecessary if constructs. Signed-off-by:
Roger Lu <roger.lu@mediatek.com> Reviewed-by:
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Matthias Brugger authored
The platform name and efuse parsing function pointer are only used while probing the device. Use them from the svs_platform_data struct instead. Reviewed-by:
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Matthias Brugger authored
Moving svs_platform_probe into driver probe function will allow us to reduce svs_platform members. This will be done in a follow-up patch. Reviewed-by:
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Matthias Brugger authored
If a compatible misses a match data entry, then something is wrong in the development phase, we don't need to check for that at runtime. Reviewed-by:
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Matthias Brugger authored
We only ever call the SoC specific probe function from svs_platform_probe. No need to carry that function in a global datastructure around. Reviewed-by:
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Roger Lu authored
Some projects might not support CONFIG_DEBUG_FS but still needs svs to be alive. Therefore, enclose debug cmd codes with CONFIG_DEBUG_FS to make sure svs can be alive when CONFIG_DEBUG_FS not supported. Signed-off-by:
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Shang XiaoJing authored
svs_init01() calls pm_runtime_get_sync() and added fail path as svs_init01_finish to put usage_counter. However, pm_runtime_get_sync() will increment usage_counter even it failed. Fix it by replacing it with pm_runtime_resume_and_get() to keep usage counter balanced. Fixes: 681a02e9 ("soc: mediatek: SVS: introduce MTK SVS engine") Signed-off-by:
Shang XiaoJing <shangxiaojing@huawei.com> Signed-off-by:
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Roger Lu authored
Add svs reset when svs_resume() fail. Fixes: a825d72f ("soc: mediatek: fix missing clk_disable_unprepare() on err in svs_resume()") Signed-off-by:
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Roger Lu authored
If svs init02 fail, it means we cannot rely on svs bank voltages anymore. We need to disable svs function and restore DVFS opp voltages back to the default voltages for making sure we have enough DVFS voltages. Fixes: 681a02e9 ("soc: mediatek: SVS: introduce MTK SVS engine") Fixes: 0bbb09b2 ("soc: mediatek: SVS: add mt8192 SVS GPU driver") Signed-off-by:
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- 30 Jan, 2023 3 commits
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Roy-CW.Yeh authored
Add MT8195 VPPSYS0 and VPPSYS1 driver data. Signed-off-by:
Roy-CW.Yeh <roy-cw.yeh@mediatek.com> Signed-off-by:
Moudy Ho <moudy.ho@mediatek.com> Reviewed-by:
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Moudy Ho authored
For MT8195, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which should be determined by compatible names. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230118031509.29834-3-moudy.ho@mediatek.comSigned-off-by:
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AngeloGioacchino Del Regno authored
This driver currently deals with GPU-SRAM regulator coupling, ensuring that the SRAM voltage is always between a specific range of distance to the GPU voltage, depending on the SoC, necessary in order to achieve system stability across the full range of supported GPU frequencies. Signed-off-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@collabora.com> Link: https://lore.kernel.org/r/20221006115816.66853-1-angelogioacchino.delregno@collabora.comSigned-off-by:
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- 25 Jan, 2023 12 commits
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Ricardo Ribalda authored
If the system does not come from reset (like when is booted via kexec()), the peripheral might triger an IRQ before the data structures are initialised. Fixes: [ 0.227710] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000f08 [ 0.227913] Call trace: [ 0.227918] svs_isr+0x8c/0x538 Signed-off-by:
Ricardo Ribalda <ribalda@chromium.org> Link: https://lore.kernel.org/r/20221127-mtk-svs-v2-0-145b07663ea8@chromium.orgSigned-off-by:
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Nancy.Lin authored
Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements which include MDP_RDMA0~7, MERGE0~3, and ETHDR. Signed-off-by:
Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by:
CK Hu <ck.hu@mediatek.com> Tested-by:
Bo-Chen Chen <rex-bc.chen@mediatek.com> Link: https://lore.kernel.org/r/20230113104434.28023-12-nancy.lin@mediatek.comSigned-off-by:
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Nancy.Lin authored
Add mtk-mutex DDP_COMPONENT_DP_INTF1 component. The MT8195 vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. It is a preparation for adding support for MT8195 vdosys1 path component. Signed-off-by:
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Nancy.Lin authored
MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Add the number of reset bits and reset base in mmsys private data. Signed-off-by:
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Nancy.Lin authored
Add mmsys for support 64 reset bits. It is a preparation for MT8195 vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. 1. Add the number of reset bits in mmsys private data 2. move the whole "reset register code section" behind the "get mmsys->data" code section for getting the num_resets in mmsys->data. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20230113104434.28023-9-nancy.lin@mediatek.comSigned-off-by:
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Nancy.Lin authored
Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Signed-off-by:
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Nancy.Lin authored
Add four mmsys config APIs. The config APIs are used for config mmsys reg. Some mmsys regs need to be set according to the HW engine binding to the mmsys simultaneously. 1. mtk_mmsys_merge_async_config: config merge async width/height. async is used for cross-clock domain synchronization. 2. mtk_mmsys_hdr_confing: config hdr backend async width/height. 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config: config mixer related settings. Signed-off-by:
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Nancy.Lin authored
Simplify code for update mmsys reg. Signed-off-by:
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Nancy.Lin authored
Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys. Signed-off-by:
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Nancy.Lin authored
Add new mmsys component: ethdr_mixer and mdp_rdma. These components will use in mt8195 vdosys1. Signed-off-by:
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Nancy.Lin authored
Add vdosys1 reset control bit for MT8195 platform. Signed-off-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Tested-by:
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Nancy.Lin authored
Add vdosys1 mmsys compatible for MT8195 platform. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Signed-off-by:
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- 19 Jan, 2023 8 commits
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Allen-KH Cheng authored
In some chipsets, we need to disable EXT_BUCK_ISO before turning on the specific power pm-domains (mtcmos), such as ADSP in MT8192 and CAM_VCORE in MT8188. Add the MTK_SCPD_EXT_BUCK_ISO flag to control the buck isolation setting in the mediatek power domain driver. Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by:
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Allen-KH Cheng authored
Add buck isolation offset and mask to power domain data. Signed-off-by:
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Fabien Parent authored
Add PMIC Keys support on MT6357 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Reviewed-by:
Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by:
Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20221005-mt6357-support-v8-6-560caaafee53@baylibre.comSigned-off-by:
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Alexandre Mergnat authored
Currently, almost all MT63XX PMIC are documented mfd/mt6397.txt. Unfortunately, the PMICs haven't always similar HW sub-features. To have a better human readable schema, I chose to make one PMIC schema to match the exact HW capabilities instead of convert mt6397.txt to mediatek,mt63xx.yaml and put a bunch of properties behind "if contain ... then ..." - add interrupt property - change property refs to match with new yaml documentation Reviewed-by:
Lee Jones <lee@kernel.org> Signed-off-by:
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Alexandre Mergnat authored
- Convert soc/mediatek/pwrap.txt to soc/mediatek/mediatek,pwrap.yaml - Add syscon compatible const for mt8186 and mt8195 to match the DTS needs, which is missing from pwrap.txt. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Fabien Parent authored
Add binding documentation for the PMIC keys on MT6357. Signed-off-by:
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Garmin.Chang authored
Add domain control data including bus protection data size change due to more protection steps in mt8188. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
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Garmin.Chang authored
Add power domains dt-bindings for MT8188. Signed-off-by:
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- 09 Jan, 2023 6 commits
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Yongqiang Niu authored
Change mtk-mmsys & mtk-mutex to modules for gki Signed-off-by:
Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by:
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Tinghan Shen authored
In the use case of configuring the access permissions of the ADSP core, the mt8186 SoC ADSP power will be switched on in the bootloader because the permission control registers are located in the ADSP subsys. Signed-off-by:
Tinghan Shen <tinghan.shen@mediatek.com> Fixes: 88590cbc ("soc: mediatek: pm-domains: Add support for mt8186") Reviewed-by:
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Nathan Lu authored
add mtk-mutex support for mt8188 vdosys0. Signed-off-by:
amy zhang <Amy.Zhang@mediatek.com> Signed-off-by:
Nathan Lu <nathan.lu@mediatek.com> Reviewed-by:
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Nathan Lu authored
1. add mt8188 mmsys 2. add mt8188 vdosys0 routing table settings Signed-off-by:
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Nathan Lu authored
modify VDOSYS0 mutex device tree Documentations for MT8188. Signed-off-by:
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Nathan Lu authored
modify VDOSYS0 mmsys device tree Documentations for MT8188. Signed-off-by:
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