- 11 Jan, 2011 40 commits
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Chris Wilson authored
As the mappable portion of the aperture is always a small subset at the start of the GTT, it is allocated preferentially by drm_mm. This is useful in case we ever need to map an object later. However, if you have a large object that can consume the entire mappable region of the GTT this prevents the batchbuffer from fitting and so causing an error. Instead allocate all those that require a mapping up front in order to improve the likelihood of finding sufficient space to bind them. Signed-off-by:Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Rather than evicting an object at random, which is unlikely to alleviate the memory pressure sufficient to allow us to continue, zap the entire aperture. That should give the system long enough to recover and reap some pages from the evicted objects, forestalling the allocation error for the new object. Signed-off-by: -
Chris Wilson authored
... and not leave the objects in a inconsistent state. Signed-off-by: -
Chris Wilson authored
Before releasing the lock in order to copy the relocation list from user pages, we need to drop all the object references as another thread may usurp and execute another batchbuffer before we reacquire the lock. However, the code was buggy and failed to clear the list... Signed-off-by: -
Chris Wilson authored
Useful for determining the layout. Signed-off-by: -
Chris Wilson authored
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Chris Wilson authored
In order to retire active buffers whilst no client is active, we need to insert our own flush requests onto the ring. This is useful for servers that queue up some rendering and then go to sleep as it allows us to the complete processing of those requests, potentially making that memory available again much earlier. Signed-off-by: -
Chris Wilson authored
Dave Airlie spotted that his ILK laptop with DMAR enabled was generating the occasional DMAR warning. "The ordering in the previous code was to rewrite the GTT table before unmapping the pages and that makes sense to me." This is his stable patch ported to d-i-n. Reported-by:
Dave Airlie <airlied@redhat.com> Original-patch-by:
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Chris Wilson authored
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Chris Wilson authored
The docs recommend that if 8 display lines fit inside the FIFO buffer, then the number of watermark entries should be increased to hide the latency of filling the rest of the FIFO buffer. Signed-off-by: -
Chris Wilson authored
... in order to avoid a BUG() and potential unbounded waits. Signed-off-by: -
Jesse Barnes authored
FDI and the transcoders can fail for various reasons, so detect those conditions and report on them. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Jesse Barnes authored
Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: -
Jesse Barnes authored
Enabling RC6 implies setting a graphics context. Make sure we do that only after the ring has been enabled, otherwise our ring commands will hang. Signed-off-by:
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Jesse Barnes authored
Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by:
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Chris Wilson authored
As the IMR for the USER interrupts are not modified elsewhere, we can separate the spinlock used for these from that of hpd and pipestats. Those two IMR are manipulated under an IRQ and so need heavier locking. Reported-and-tested-by:
Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by:
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Chris Wilson authored
... and move it under the spinlock to gain the appropriate memory barriers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32752Signed-off-by:
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Chris Wilson authored
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Chris Wilson authored
Otherwise we may consume 20% of the CPU just handling IRQs whilst rendering. Ouch. Signed-off-by: -
Chris Wilson authored
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Chris Wilson authored
We need to ensure that writes through the GTT land before any modification to the MMIO registers and so must impose a mandatory write barrier when flushing the GTT domain. This was revealed by relaxing the write ordering by experimentally mapping the registers and the GATT as write-combining. Signed-off-by: -
Chris Wilson authored
As has_gem is unconditionally set to true, the conditional immediately following that assignment is superfluous. Signed-off-by: -
Jesse Barnes authored
These functions need to be reworked for Ironlake and above, but until then at least avoid reading non-existent registers. Signed-off-by:
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Chris Wilson authored
When bringing up new hardware, or otherwise experimenting, GPU hangs are a way of life. However, the automatic GPU reset can do more harm than good under these circumstances, as we may wish to capture a full trace for debugging. Based on a patch by Zhenyu Wang. Signed-off-by: -
Yuanhan Liu authored
On Ironlake, the LP0 latency is hardcoded and in ns unit, while on Sandybridge, it comes from a register and with unit 0.1 us. So, fix the wrong latency value while computing wm0 on Ironlake and Sandybridge. Signed-off-by:
Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by:
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Jesse Barnes authored
This patch actually makes the watermark code even uglier (if that's possible), but has the advantage of sharing code between SNB and ILK at least. Longer term we should refactor the watermark stuff into its own file and clean it up now that we know how it's supposed to work. Supporting WM2 on my Vaio reduced power consumption by around 0.5W, so this patch is definitely worthwhile (though it also needs lots of test coverage). Signed-off-by:
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Chris Wilson authored
Flush the chipset write buffers before and after adjusting the GTT base register, just in case. We only modify this value upon initialisation (boot and resume) so there should be no outstanding writes, however there are always those persistent PGTBL_ER that keep getting reported upon resume. Signed-off-by: -
Chris Wilson authored
On i830 if the tail pointer is set to within 2 cachelines of the end of the buffer, the chip may hang. So instead if the tail were to land in that location, we pad the end of the buffer with NOPs, and start again at the beginning. Signed-off-by: -
Chris Wilson authored
There should be no difference, but we can eliminate redundant code. Signed-off-by: -
Jesse Barnes authored
In some configuration, the PCU may allow us to overclock the GPU. Check for this case and adjust the max frequency as appropriate. Also initialize the min/max frequencies to default values as indicated by hardware. Signed-off-by:
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Chris Wilson authored
... and just any combination of bits & ~PFIT_ENABLE. This way we do not attempt disable to the panel fitter controller uselessly upon intel_lvds_disable(). Signed-off-by: -
Chris Wilson authored
By tracking the current status of the backlight we can prevent recording the value of the current backlight when we have disabled it. And so prevent restoring it to 'off' after an unbalanced sequence of intel_lvds_disable/enable. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=22672Tested-by:
Alex Riesen <raa.lkml@gmail.com> Tested-by:
Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by:
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Chris Wilson authored
Alex Fiestas reported an issue with his HDMI connector being misdetected as DVI unless he had something connected upon boot. By moving the decision as to whether to use HDMI or DVI encoding for the HDMI capable output until we probe the monitor means that we should avoid sending a HDMI signal to a DVI monitor and also correctly detect hardware like Alex's. However, to really determine what connector is soldered onto the wire we need to inspect the VBT sdvo child devices - but can we trust it? Reported-by:
Alex Fiestas <alex@eyeos.org> Tested-by:
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Yuanhan Liu authored
Some voltage swing/pre-emphasis level use the same value on eDP Sandybridge, like 400mv_0db and 600mv_0db are with the same value of (0x0 << 22). So, fix them, and point out the value if it isn't a supported voltage swing/pre-emphasis level. Signed-off-by:
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David Müller authored
Since Linux 2.6.36 the digital output on my system (855GME + DVI-I) is not working any longer. The analog output is always activated regardless of the type of monitor attached. The culprit seems to be intel_crt_detect_ddc(), which returns true as soon as an ACK from the EDID device is received. Obviously this approach does not work with DVI-I where the analog and digital outputs share a common DDC bus. In a similar manner to the shared DDC wire, ala the "Mac Mini Hack", we need an additional check to make sure that there really is an analog device attached to the DDC. Signed-off-by:
David Müller <d.mueller@elsoft.ch> Signed-off-by:
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Jesse Barnes authored
When trying to do channel equalization, we need to make sure we still have clock recovery on all lanes while training. We also need to try clock recovery again if we lose the clock or if channel eq fails 5 times. We'll try clock recovery up to 5 more times before giving up entirely. Gets suspend/resume working on my Vaio again and brings us back into compliance with the DP training sequence spec. Signed-off-by:
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Jesse Barnes authored
We were using a stale pointer in the check which caused us to use CPU attached DP params when we should have been using PCH attached params. Signed-off-by:
Jan-Hendrik Zab <jan@jhz.name> Tested-by:
Christoph Lukas <christoph.lukas@gmx.net> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6Linus Torvalds authored
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (390 commits) drm/radeon/kms: disable underscan by default drm/radeon/kms: only enable hdmi features if the monitor supports audio drm: Restore the old_fb upon modeset failure drm/nouveau: fix hwmon device binding radeon: consolidate asic-specific function decls for pre-r600 vga_switcheroo: comparing too few characters in strncmp() drm/radeon/kms: add NI pci ids drm/radeon/kms: don't enable pcie gen2 on NI yet drm/radeon/kms: add radeon_asic struct for NI asics drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init drm/radeon/kms: add ucode loader for NI drm/radeon/kms: add support for DCE5 display LUTs drm/radeon/kms: add ni_reg.h drm/radeon/kms: add bo blit support for NI drm/radeon/kms: always use writeback/events for fences on NI drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5 drm/radeon/kms: add backend map workaround for barts drm/radeon/kms: fill gpu init for NI asics drm/radeon/kms: add disabled vbios accessor for NI asics drm/radeon/kms: handle NI thermal controller ...
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git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/stagingLinus Torvalds authored
* 'i2c-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging: i2c: Constify i2c_client where possible i2c-algo-bit: Complain about masters which can't read SCL i2c-algo-bit: Refactor adapter registration i2c: Add generic I2C multiplexer using GPIO API i2c-nforce2: Remove unnecessary cast of pci_get_drvdata i2c-i801: Include <linux/slab.h>
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git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfinLinus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (52 commits) Blackfin: encode cpu-rev into uImage name Blackfin: bf54x: don't ack GPIO ints when unmasking them Blackfin: sram_free_with_lsl: do not ignore return value of sram_free Blackfin: boards: add missing "static" to peripheral lists Blackfin: DNP5370: new board port Blackfin: bf518f-ezbrd: fix dsa resources Blackfin: move "-m elf32bfin" to general LDFLAGS Blackfin: kgdb_test: make sure to initialize num2 Blackfin: kgdb: disable preempt schedule when running single step in kgdb Blackfin: kgdb: disable interrupt when single stepping in ADEOS Blackfin: SMP: kgdb: apply anomaly 257 work around Blackfin: fix building IPIPE code when XIP is enabled Blackfin: SMP: kgdb: flush core internal write buffer before flushinv Blackfin: sport_uart resources: remove unused secondary RX/TX pins Blackfin: tll6527m: fix spelling in unused code (struct name) Blackfin: bf527-ezkit: add adau1373 chip address Blackfin: no-mpu: fix masking of small uncached dma region Blackfin: pm: drop irq save/restore in standby and suspend to mem callback MAINTAINERS: update Analog Devices support info Blackfin: dpmc.h: pull in new pll.h ...
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