- 30 Mar, 2017 40 commits
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Ken Wang authored
Newer asics need 64 bit writeback slots. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Ken Wang authored
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by:
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Junwei Zhang authored
v2: agd: move apertures to mc structure Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Daniel Vetter authored
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
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Daniel Vetter authored
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
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Andres Rodriguez authored
This information is intended to provide the required data to associate amdgpu tracepoints with their corresponding dma_fence_* events. Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Andres Rodriguez authored
Most of the traces have uniform format except for two of them. Having all the traces match makes it simple to run awk on the ftrace output. Reviewed-by:
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Xiangliang Yu authored
Because different HWs have different definition for CE & DE meta data, follow mqd design to move the structures to vi_structs.h. And change the prefix from amdgpu to vi as the structures is only for VI family. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
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Junshan Fang authored
Signed-off-by:
Junshan Fang <Junshan.Fang@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Was missed when polaris12 support was added. Signed-off-by: -
Christian König authored
Not used in a while. Signed-off-by:
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Eric Huang authored
Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
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Eric Huang authored
Disable avfs to make voltage change take effect. Signed-off-by:
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Andy Shevchenko authored
There is no need to repeat information that printed by PCI core at boot time. Besides that printing was potentially wrong since resource_size_t might be bigger than 32 bits and there is a dedicated specifier for such type, i.e. %pap. Someone can fix it and use even better approach, i.e. %pR. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
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Rex Zhu authored
v2: fix merge error. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by:
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Christian König authored
We completely bypass the HDP now. Signed-off-by:
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Joe Perches authored
Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Joe Perches authored
Using 'printk("\n")' is not preferred anymore and using printk to continue logging messages now produces multiple line logging output unless the continuations use KERN_CONT. Convert these uses to appropriately use pr_cont or a single printk where possible. Miscellanea: o Use a temporary const char * instead of multiple printks o Remove trailing space from logging by using a leading space instead Signed-off-by: -
Alex Deucher authored
There still seem to be some blocks that make accesses in the lower part of the address space. This works around this. Reviewed-by:
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Alex Deucher authored
Program the VCE BAR and offsets properly. The current code was carried over from a limitation from older VCE versions. Reviewed-by:
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Joe Perches authored
To enable eventual removal of pr_warning This makes pr_warn use consistent for drivers/gpu Prior to this patch, there were 15 uses of pr_warning and 20 uses of pr_warn in drivers/gpu Acked-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Geert Uytterhoeven authored
Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: dri-devel@lists.freedesktop.orgamd-gfx@lists.freedesktop.org Signed-off-by:
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Lyude authored
Aux transfers always fail with non-zero status flags when there's nothing connected on the port, so we don't usually need to see all of the debugging information from it. Also, we try reprobing a -lot-, so without ratelimiting most of the kernel log is filled up with messages from radeon_dp_aux_transfer_native. Signed-off-by:
Lyude <lyude@redhat.com> Signed-off-by:
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Alex Deucher authored
This enables the LEDs that light up based on DPM states on some Fiji boards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=97590Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Junwei Zhang authored
Signed-off-by:
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Trigger Huang authored
In some cases, manually insmod/rmmod amdgpu is necessary. When unloading amdgpu, the KIQ IRQ enable/disable function will case system hang. The root cause is, in the sequence of function amdgpu_fini, the sw_fini of IP block AMD_IP_BLOCK_TYPE_GFX will be invoked earlier than that of AMD_IP_BLOCK_TYPE_IH. So continue to use the variable freed by AMD_IP_BLOCK_TYPE_GFX will cause system hang. Signed-off-by:
Trigger Huang <trigger.huang@amd.com> Reviewed-by: Xiangliang Yu < Xiangliang.Yu@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Acked-by:
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Alex Deucher authored
v2: agd: bump version Reviewed-by:
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Junwei Zhang authored
v2: move the config struct to drm_amdgpu_info_device v3: move the config feature to amdgpu_gca_config Signed-off-by:
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Xiangliang Yu authored
Need to free mqd backup when destroying ring. Signed-off-by:
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Xiangliang Yu authored
When send messages to hypervior, the messages format should be is idh_request, not idh_event. Signed-off-by:
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Xiangliang Yu authored
vi_mqd is only used by VI family but mqd_ptr and mqd_backup is common for all ASIC, so change the pointer to void. Signed-off-by:
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Monk Liu authored
v2: use in_rest to fix compute ring test failure issue which occured after FLR/gpu_reset. we need backup a clean status of MQD which was created in drv load stage, and use it in resume stage, otherwise KCQ and KIQ all may faild in ring/ib test. Signed-off-by:
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Monk Liu authored
In resume routine, we need clr RB prior to the ring test of engine, otherwise some engine hang duplicated during GPU reset. Signed-off-by:
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Monk Liu authored
we can use it clear ring buffer instead of fullfill 0, which is not correct for engine Signed-off-by:
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Monk Liu authored
this is required for restoring the mqds after GPU reset. Signed-off-by:
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Monk Liu authored
use it to seperate driver load and gpu reset/resume because gfx IP need different approach for different hw_init trigger source Signed-off-by:
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Monk Liu authored
this flag will get cleared by request gpu access Signed-off-by:
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Monk Liu authored
no need to use a delay work since we don't know how much time hypervisor takes on FLR, so just polling and waiting in a work. Signed-off-by:
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Monk Liu authored
Use no kiq version reg access due to: 1) better performance 2) INTR context consideration (some routine in mailbox is in INTR context e.g.xgpu_vi_mailbox_rcv_irq) Signed-off-by:
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