- 15 Feb, 2016 1 commit
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Michael Turquette authored
Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
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- 12 Feb, 2016 6 commits
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Rajendra Nayak authored
With gdsc driver capable of handling hierarchical power domains, specify oxili_gdsc as parent of oxilicx_gdsc. Remove all direct calls to genpd from the mmcc clock driver. The adding and removing of subdomains is now handled from within the gdsc driver. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Rajendra Nayak authored
Add all gdsc data which are part of mmcc on msm8996 family Signed-off-by:
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Rajendra Nayak authored
Add all data for the GDSCs which are part of msm8996 GCC block Signed-off-by:
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Rajendra Nayak authored
Some gdscs might be controlled via voting registers and might not really disable when the kernel intends to disable them (due to other votes keeping them enabled) Mark these gdscs with a flag for we do not check/wait on a disable status for these gdscs within the kernel disable callback. Also at boot, if these GDSCs are found to be ON, we make sure we vote for them before we inform the genpd framework about their status. If genpd gets no users, it then disables (removes the vote) them as part of genpd_poweroff_unused() Signed-off-by:
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Rajendra Nayak authored
Some gdsc power domains can have a gds_hw_controller block inside to help ensure all slave devices within the power domain are idle before the gdsc is actually switched off. This is mainly useful in power domains which host a MMU, in which case its necessary to make sure there are no outstanding MMU operations or pending bus transactions before the power domain is turned off. In gdscs with gds_hw_controller block, its necessary to check the gds_hw_ctrl status bits instead of the ones in gdscr, to determine the state of the powerdomain. While at it, also move away from using jiffies and use ktime APIs instead for busy looping on status bits. Signed-off-by:
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Rajendra Nayak authored
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs specify the parents (if any) and the driver add genpd subdomains for them. Signed-off-by:
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- 10 Feb, 2016 4 commits
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Sylvain Lemieux authored
This patch add the support to setup the HCLK PLL output using the "assigned-clock-rates" parameter in the device tree. If the option is not use, the clock setup by the kickstart and/or bootloader remain unchanged. The previous kernel version did not change the clock frequency output setup by the kickstart and/or bootloader; this version always setup the clock frequency output to 208MHz. Signed-off-by:
Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: versatile: mask VCO bits before writing
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Linus Walleij authored
The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3 ("clk: versatile-icst: convert to use regmap") Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Sylvain Lemieux authored
The following errors are display in the console during the power-on: [ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12 [ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12 There is no need to register clock "0"; the first clock used is 1; Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> [sboyd@codeaurora.org: s/prepare/register/] Signed-off-by:
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- 09 Feb, 2016 3 commits
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Masahiro Yamada authored
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"), __clk_init_parent() called .get_parent() only for multi-parent clocks. That commit changed the behavior to call .get_parent() if available even for single-parent clocks and root clocks. It turned out a problem because there are some single-parent clocks that implement .get_parent() callback and return non-zero index. The SOCFPGA clock is the case; the commit broke the SOCFPGA boards. To keep the original behavior, invoke .get_parent() only when num_parents is greater than 1. Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()") Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
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Sudip Mukherjee authored
We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by:
Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by:
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Sudip Mukherjee authored
Add a helper function devm_add_action_or_reset() which will internally call devm_add_action(). But if devm_add_action() fails then it will execute the action mentioned and return the error code. Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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- 08 Feb, 2016 6 commits
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Andreas Färber authored
As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869 ("clk: meson: Add support for Meson clock controller") Signed-off-by:
Andreas Färber <afaerber@suse.de> Acked-by:
Carlo Caione <carlo@endlessm.com> Signed-off-by:
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Arnd Bergmann authored
clang found a bug with the __socfpga_pll_init definition: drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and global variables This moves the __init annotation to the right place so the function actually gets discarded. Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Mike Looijmans authored
There are two TI CDCE clock chips in this file. Move them close together so they're easier to find. No functional change, just cosmetic. Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Alphabetize] Signed-off-by:
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Mike Looijmans authored
Simple cosmetic fix. Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
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Stephen Boyd authored
Merge tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull tegra fixes from Thierry Reding: clk: tegra: Fixes for v4.5-rc3 This set contains a bunch of miscellaneous fixes that have accumulated over the past couple of weeks, primarily for the Tegra210 support added in v4.5-rc1. * tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
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- 07 Feb, 2016 3 commits
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Stephen Boyd authored
These functions either never existed or were only used in OF_CLK_DECLARE() macros. Remove the dead prototypes. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: -
Stephen Boyd authored
We don't use CLK_IS_ROOT but in a few places in the common clk framework core. Let's replace those checks with a check for the number of parents a clk has instead of the flag, freeing up one flag for something else. We don't remove the flag yet so that things keep building, but we'll remove it once all drivers have removed their flag usage. Signed-off-by: -
Stephen Boyd authored
clk_get() for DT based clks already returns EPROBE_DEFER when the OF clk provider is not present. So having all this code in the clk provider to return EPROBE_DEFER when the gpio isn't ready yet can be replaced with a platform driver that doesn't add the clk provider until the gpio can be requested. Get rid of the OF_CLK_DECLARE and convert this to a platform driver instead. Tested-by:
Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon@solid-run.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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- 04 Feb, 2016 3 commits
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Heiko Stuebner authored
Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by:Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
Add a clock type for fixed factor clocks. This allows us to define fixed factor clocks where they appear in the clock hierarchy instead of in the init function. The additional factor_gate type, finally allows us to model some last parts of the clock tree correctly. Signed-off-by: -
Heiko Stuebner authored
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock hclk_vcodec_pre in between and not a child of hclk_disp_pre. Signed-off-by:
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- 02 Feb, 2016 14 commits
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Shawn Lin authored
Add free memeory if rockchip_clk_register_branch fails. Fixes: a245fecb ("clk: rockchip: add basic infrastructure...") Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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Insu Yun authored
If clock is already unregistered, it returns with holding lock. It needs to be unlocked. Signed-off-by:
Insu Yun <wuninsu@gmail.com> [sboyd@codeaurora.org: Use goto instead] Signed-off-by:
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Arnd Bergmann authored
The clk-vt8500.c driver would previously enter an endless loop when invalid settings got requested, this was now fixed. However, the driver will now return uninitialized data for a subset of those cases instead, as the gcc correctly warns: clk/clk-vt8500.c: In function 'wm8650_find_pll_bits': clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor2 = best_div2; ^ clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor1 = best_div1; ^ clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized] *multiplier = best_mul; This reworks the error handling in the driver so we now return -EINVAL from clk_round_rate() and clk_set_rate() when we get impossible inputs. Signed-off-by: -
Masahiro Yamada authored
If clk_fetch_parent_index() fails, p_rate is unused. Move the assignment after the error checking. Signed-off-by:
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Masahiro Yamada authored
The clk_core_get_parent_by_index can be used as a helper function to simplify the implementation of clk_fetch_parent_index(). Signed-off-by:
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Masahiro Yamada authored
If parent is given with NULL, clk_fetch_parent_index() could return a positive index value. Currently, parent is checked by the callers of this function, but it would be safer to do it in this function. Signed-off-by:
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Masahiro Yamada authored
This loop can be much simpler. If a new parent is available for orphan clocks, __clk_init_parent(orphan) can detect it. Signed-off-by:
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Masahiro Yamada authored
Currently, clk_register() never checks a circular parent looping, but clock providers could register such an insane clock topology. For example, "clk_a" could have "clk_b" as a parent, and vice versa. In this case, clk_core_reparent() creates a circular parent list and __clk_recalc_accuracies() calls itself recursively forever. The core infrastructure should be kind enough to bail out, showing an appropriate error message in such a case. This helps to easily find a bug in clock providers. (uh, I made such a silly mistake when I was implementing my clock providers first. I was upset because the kernel did not respond, without any error message.) This commit adds a new helper function, __clk_is_ancestor(). It returns true if the second argument is a possible ancestor of the first one. If a clock core is a possible ancestor of itself, it would make a loop when it were registered. That should be detected as an error. Signed-off-by:
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Masahiro Yamada authored
The translation from the index into clk_core is done by clk_core_get_parent_by_index(). The if-block for num_parents == 1 case is duplicating the code in the clk_core_get_parent_by_index(). Drop the "if (num_parents == 1)" from the special case. Instead, set the index to zero if .get_parent() is missing. Signed-off-by:
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Masahiro Yamada authored
The .get_parent is mandatory for multi-parent clocks. Move the check to __clk_core_init(), like other callback checkings. Signed-off-by:
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Jon Hunter authored
Sparse reports the following warnings for structures and functions that should be declared static: drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol 'tegra_super_gen_info_gen4' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol 'tegra_super_gen_info_gen5' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol 'tegra_super_clk_init' was not declared. Should it be static? Fix this by making the above static. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Jon Hunter authored
Sparse reports the following warnings for functions in clk-tegra210.c that should be declared as static: drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol 'tegra210_pllcx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol '_pllc_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol '_pllc2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol '_pllc3_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol '_plla1_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol 'tegra210_plla_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol 'tegra210_plld_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol 'tegra210_plld2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol 'tegra210_plldp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol 'tegra210_pllc4_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol 'tegra210_pllre_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol 'tegra210_pllx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol 'tegra210_pllmb_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol 'tegra210_pllp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol 'tegra210_pllu_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol 'tegra210_clk_adjust_vco_min' was not declared. Should it be static? Fix this by declaring the above as static. Signed-off-by:
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Jon Hunter authored
Sparse generates the following warning for the pll_m params structure: drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry defined twice drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here Fix this by correcting the index for the MISC1 register. Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks") Signed-off-by: -
Jon Hunter authored
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined but not used and when the OVERRIDE bit is cleared in tegra210_pll_init() the code directly uses the bit number. Therefore, use the definition, PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit. Signed-off-by:
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